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muh-bot
11032fe95e [muh] delay v2 完成: 全部 8 个 lookback 算法改为 no_delay 
基于 CCCL single_pass_scan_operators.cuh 源码分析:
  delay() 在 gridDim.x < 500 时只做 __threadfence_block，不 __nanosleep
  BI-V100: 16 SMs → max 32 CTAs → 永远 < 500

变更文件:
  tuning_reduce_by_key.cuh: 全部 66 条 → no_delay (已在上个 commit)
  tuning_scan_by_key.cuh: 全部 ~76 条 → no_delay (已在上个 commit)
  tuning_select_if.cuh: 38 个 scale_delay() → nd(l2w), 删除 scale_delay 函数
  tuning_unique_by_key.cuh: 31 个 sd() → nd(l2w), 删除 sd 函数
  tuning_three_way_partition.cuh: 6 个 sd() → nd(l2w)
  tuning_rle_encode.cuh: 5 个 sd() → nd(l2w)
  tuning_rle_non_trivial_runs.cuh: 5 个 sd() → nd(l2w)
  tuning_scan.cuh: 12 个 exponential_* → no_delay

L2WriteLatency 全部保留 (CCCL 构造函数一次性 L2 write 等待)
threads/items/load_algorithm/load_modifier 不变 (CCCL benchmark-tuned)
 2026-08-04 07:18:48 +00:00
muh-bot
a898faa34e [muh] delay v2: reduce_by_key + scan_by_key 全部改为 no_delay 
基于 CCCL delay 系统源码分析 (single_pass_scan_operators.cuh):
  if (gridDim.x < 500) __threadfence_block();  // 小 grid
  else __nanosleep(Delay);                      // 大 grid

BI-V100: 16 SMs × ~2 CTAs/SM = max 32 CTAs → gridDim.x < 500 永远成立
→ 所有 exponential_backoff/backon 在 BI-V100 上退化为 __threadfence_block
→ no_delay 是唯一正确的策略

变更:
- tuning_reduce_by_key.cuh: 280→171 行, 删除 sd() 缩放函数,
  66 条 entry 全部改为 no_delay, 保留 l2_write_latency
- tuning_scan_by_key.cuh: 256→145 行, 同上
- CCCL benchmark-tuned 的 threads/items/load_algorithm 不变
 2026-08-04 07:17:34 +00:00
dylanyunlon
31d39e6032 [muh] 首批 BI-V100 实测数据写入 3 个 tuning headers: scan/topk/transform 
这是项目历史上第一次用真实 benchmark 数据替换拍脑袋参数。

scan.cuh — bi100_lookback_4B_o4:
  实测: dcid_0.ipt_22.l2w_500.ld_0.ns_1904.tpb_384.trp_1
  speedups: 1.038085 1.009473 1.007679 1.005803  SMEM=33792 (69%)
  关键发现: ns×0.5 假设是错的。实测最优 ns=1904 (和 SM100 原值相同)。
  dcid=0 (no_delay) 胜过 dcid=6 (exponential_backon_jitter)。
  原因: 16 SMs = ~32 CTAs, lookback contention 极小, 不需要 delay 策略。
  改动: delay 从 {exponential_backon_jitter, 952, 498} → {no_delay, 1904, 500}

topk.cuh:
  实测: ipt_4.ld_0.tpb_512  speedups: 1.039611 1.000222 1.004295
  确认 CCCL SM90+ 公式 (items=4*4/key_size=4, threads=512) 在 BI-V100 上也是最优。
  ld=0 (LOAD_DEFAULT) 胜过 ld=1 at small sizes。
  ipt=16 在 32K+ 明显回退 → items 不能太大。

transform.cuh — bytes_in_flight:
  实测: alg_1.bif_8.pref_2.tpb_256.unrl_1.vsp2_1  1.203199 1.058919 1.019168
  bif=8 (64KB) 全面胜过 bif=0 (32KB) 和 bif=-8 (16KB)。
  Top 30 结果全部是 bif=8 → 高置信度。
  改动: bi100_bytes_in_flight 从 32KB → 64KB。
  物理解释: 56 GB/s per SM × ~1100ns HBM latency ≈ 62KB, 和 64KB 吻合。

跨算法发现:
  - BI-V100 的 16 SMs 使得 inter-CTA contention 很低
  - CCCL 的 delay 策略 (为 80-148 SMs 设计) 在 16 SMs 上过度保守
  - 各算法的 threads/items 最优值和 SM100 接近, 但 delay/bif 参数差异大
 2026-08-04 07:13:01 +00:00
project_6
475574fd3d [muh] bench_triton_real + bi100_configs: REAL tunable surface benchmark 
TUNING_SURFACE_TRUTH.md identified the 5 ACTUAL tunable surfaces on BI-V100
(ixformer pre-compiled kernels ignore CUB-style params). This commit adds
tools targeting those real surfaces:

New files:
- muh/bench_triton_real.py: Benchmark with ACTUAL parameter injection into
  Triton JIT kernels (prefix_prefill BLOCK/WARPS, flash_attn configs, MoE M)
- muh/bi100_triton_configs.py: SMEM-safe triton.Config generator (SM=16)
- muh/bi100_configs.json: 22 flash_attn + 9 prefill + 5 MoE candidate configs

SMEM formula: Q_resident + K_per_iter + softmax_state (not naive Q+K+V+acc).
BLOCK_M=128 fits at 85% SMEM utilization with head_dim=128.
 2026-08-04 06:19:07 +00:00
Claude
5747e7c290 [docs] BI-V100 benchmark runbook: Phase 0 硬件探测 + Phase 1 quick sweep + Phase 3 端到端验证 2026-08-04 01:14:30 +00:00
dylanyunlon
12ad7a3190 [muh] 7 headers 完整移植 CCCL tuning tables: segmented_sort 7%→29%, merge_sort 22%→43%, merge 30%→49%, adjacent_difference 38%→65%, batch_memcpy 37%→41%, find 35%→43%, find_bound 31%→44% 
每个文件都是直接 cat 读完整 CCCL 源码后理解全部参数语义，
然后用大模型生成 BI-V100 适配版本。不使用 grep/sed/批量脚本。

segmented_sort.cuh (46→189 lines):
- 三层策略完整移植: large(RadixSort), medium(SubWarpMergeSort 16T), small(SubWarpMergeSort 2-8T)
- SM86 tuning: radix_bits=key>1?6:4, scale_reg_bound(256,23)
- BI-V100 SMEM cap for all three tiers

merge_sort.cuh (43→83 lines):
- SM50{256,11} SM52{512,15} SM60+{256,17} 三代参数
- nominal_4b_items_to_items scaling + unroll flag

merge.cuh (55→89 lines):
- SM52/SM60/SM80/SM90/SM100 五代参数
- bulk_copy=false (BI-V100 无 cp.async.bulk)

adjacent_difference.cuh (46→77 lines):
- nominal_8b_items_to_items(7) scaling
- may_alias → LOAD_CA vs LOAD_LDG

batch_memcpy.cuh (86→95 lines):
- small{128T,4buf,8B} + large{256T,32B} 双策略
- prefer_pow2_bits=false (SM70+)

find.cuh (32→39 lines):
- scale_mem_bound(128,16) + vec_size=4

find_bound_sorted_values.cuh (33→47 lines):
- SM80+: {512, N4B(15)} / SM60+: {256} / SM50: LOAD_LDG
 2026-08-03 21:36:50 +00:00
muh-bot
2badbfa1b9 merge: resolve conflicts, keep full CCCL port versions 2026-08-03 21:35:31 +00:00
muh-bot
c7ff12c28d [muh] scan_by_key 14%→13%, rle_non_trivial_runs 7%→10%, rle_encode 9%→10%: 从 CCCL 3325 行源码完整移植 
tuning_scan_by_key.cuh: 284→256 行 (更紧凑但保留全部 ~76 条 entries)
  - SM100: 16 条 benchmark entries (key 1-8B × value 1-8B, 含 LOAD_CA)
  - SM90: ~30 条 (key 1-16B × value 1-16B, 含 int128)
  - SM80: ~30 条 (完整 fallback)
  - 7-field policy: 比 reduce_by_key 多 store_algorithm
  - vllm 热路径: key=4B value=4B (paged_attention prefix-sum)

tuning_rle_non_trivial_runs.cuh: 46→68 行
  - SM100: 4 条 (key 1/2/4/8B, double 回退 SM90)
  - SM90: 5 条 (含 int128 key=16B)
  - 额外字段: store_with_time_slicing (all false)

tuning_rle_encode.cuh: 54→63 行
  - SM100: 4 条, SM90: 5 条, SM80: 5 条
  - 结构同 reduce_by_key (6-field policy)
 2026-08-03 21:35:16 +00:00
dylanyunlon
6a56649d9a [muh] radix_sort 6%→19%, rle_encode 8%→21%, rle_non_trivial_runs 6%→18%: 完整移植 CCCL SM90/SM100 tuning tables + BI-V100 SMEM 48KB 约束 
radix_sort.cuh (148→461 lines):
- 完整 get_sm90_tuning() + get_sm100_tuning() 含 benchmark annotations
- bi100_smem_cap() SMEM 48KB 约束 + reg_scale_onesweep()
- policy_selector: onesweep(key>=4B) / multi_pass(key<4B)

rle_encode.cuh (54→134 lines):
- SM80/SM90/SM100 三代完整参数 + BI-V100 delay scaling (ns×0.5, l2w×0.6)

rle_non_trivial_runs.cuh (46→128 lines):
- SM80/SM90/SM100 三代完整参数 + key=8B(double) SM90 fallback
 2026-08-03 13:14:57 +00:00
muh-bot
1b74226910 [muh] reduce_by_key 12%→16%: 从 CCCL 1735 行源码完整移植 66 条 SM80/SM90/SM100 tuning entries 
tuning_reduce_by_key.cuh: 203→280 行
- SM100: 16 条 (key 1-8B × accum 1-8B, 带原始 benchmark 注释)
- SM90:  25 条 (key 1-16B × accum 1-16B)
- SM80:  25 条 (完整 fallback chain)
- vllm 热路径标注: key_size=4, accum_size=4 (paged_attention score reduction)
- SMEM overflow while-loop 保护
- SM100 delay 缩放 ns*0.5, l2w*0.6
- 保留 CCCL float32 regression 注释 (key=2B accum=4B accum_t==float32)
 2026-08-03 13:11:31 +00:00
muh-bot
5923223cba [muh] three_way_partition 7%→13%, histogram 13%→21%: 继续从 CCCL 源码移植 SM80/SM90/SM100 tuning tables 
tuning_three_way_partition.cuh: 58→99 行
  - 移植 SM100 (5 entries) + SM90 (10) + SM80 (4) 共 19 条
  - 按 (offset_size, input_size) 二维分派
  - 三路划分 SMEM: 3 * tpb * ipt * input_size

tuning_histogram.cuh: 48→76 行
  - 移植 SM100 (2 entries) + SM90 (2) + default
  - privatized SMEM bins 保护
  - 保留 CCCL benchmark 注释
 2026-08-03 13:02:58 +00:00
muh-bot
c350c1c7e5 [muh] select_if 5%→17%, unique_by_key 3%→11%: 从 CCCL 源码完整移植 SM80/SM90/SM100 三代 tuning table 
tuning_select_if.cuh: 139→454 行
  - 移植 CCCL 全部 82 个 benchmark-tuned 入口
  - 保留 may_alias/flagged/keep_rejects/distinct_partitions 四维分派
  - SM100 entries 带原始 benchmark 注释 (ipt_N.tpb_M.ns_X.dcid_Y.l2w_Z speedups)
  - SMEM overflow while-loop 保护 (48KB cap)
  - delay 缩放 ns*0.5, l2w*0.6

tuning_unique_by_key.cuh: 52→166 行
  - 移植 SM80 (32 entries) + SM90 (24 entries) + SM100 (15 entries) 共 71 条
  - 按 (key_size, value_size) 全组合分派
  - SMEM 安全检查: tile = tpb * ipt * (key_sz + val_sz)
 2026-08-03 13:01:11 +00:00
muh-bot
24ef6a91b5 [CCCL] 瘦身 + 补全: 移除 cudax/python/libcudacxx-tests 冗余文件, 新增 c2h 测试助手 + cmake 构建系统 + 8 个 CUDA thrust examples 
变更摘要:
- 删除: cudax/ (783 files, 7.2M) — 实验性组件，竞赛不需要
- 删除: python/ (226 files, 2.0M) — Python 绑定，竞赛不需要
- 删除: libcudacxx/{test,benchmarks,codegen,cmake,share} (4432 files, 31M)
  保留: libcudacxx/include/ (1463 headers, cuda::std 编译依赖)
- 新增: c2h/ (27 files) — CUB Catch2 测试辅助头文件，编译 243 个测试必需
- 新增: cmake/ (29 files) — CCCL 原生 CMake 构建系统
- 新增: thrust/examples/cuda/ (7 files) + cpp_integration/ (1 file)
  async_reduce, custom_temporary_allocation, explicit_cuda_stream,
  global_device_vector, range_view, unwrap_pointer, wrap_pointer, device

结果: cccl_upstream 从 74M→35M (瘦身 53%), 核心内容 100% 保留:
  27/27 tuning headers, 78 benchmarks, 243 tests,
  60 thrust examples, 18 CUB examples, 全部编译头文件
 2026-08-03 12:39:26 +00:00
Claude
a2a5dd8f00 feat: asymmetric BLOCK_M/BLOCK_N search + re-add BI-V100 autotune configs 
bench_triton_prefill.py:
  - Split --block into --block (BLOCK_M) and --block-n (BLOCK_N)
  - Each (M, N, warps) combo triggers Triton JIT recompilation
  - Enables finding asymmetric optima like M=64,N=32 that save SMEM

triton_flash_attention.py:
  - Re-add 3 BI-V100 autotune configs (64x32, 32x64, 64x64 with warps=4)
  - These were wrongly reverted in 8c1955d -- autotune is zero-risk

run_on_bi100.sh:
  - Updated to use asymmetric block search
 2026-08-03 11:18:18 +00:00
dylanyunlon
fe64650681 add muh/run_on_bi100.sh — single-paste diagnostic + benchmark for Phanthy Cloud 
8 steps in sequence, no user interaction needed:
1. Hardware diagnostics (SM count, SMEM, VRAM per GPU)
2. SMEM 32KB vs 48KB definitive answer from torch.cuda.get_device_properties
3. Triton availability check
4. prefix_prefill kernel import test
5. Triton compilation smoke test (compile+run trivial kernel)
6. Actual prefill kernel benchmark: 16 variants × 4 ctx_lens
7. Show current computility-run.yaml
8. fused_moe BLOCK_SIZE_M dispatch table for Qwen3.6 dimensions
 2026-08-03 10:51:20 +00:00
dylanyunlon
327497dc17 feat(muh): add bench_triton_prefill.py — real compile-time param injection benchmark 
Unlike bench_bi100.py which called torch.sum() without injecting params:
- Directly invokes prefix_prefill._fwd_kernel Triton JIT kernel
- Each (BLOCK, NUM_WARPS) constexpr pair triggers Triton recompilation
  into a different kernel binary — same mechanism as CCCL #define TUNE_*
- Combos that exceed SMEM fail at compile time (caught, reported as COMPILE FAIL)
- Measures actual kernel execution time per compiled variant
- Outputs speedup vs baseline (BLOCK=64, WARPS=4) in CCCL format

Search space: BLOCK=[16,32,64,128] × WARPS=[1,2,4,8] = 16 variants
Problem sizes: ctx_len=[128,512,2048,8192] (Qwen3.6 typical workloads)
Test tensors match Qwen3.6: head_dim=128, num_heads=64, num_kv_heads=8 (GQA)

Requires GPU — will error immediately if no CUDA device available.
Reports GPU properties (SM count, SMEM, VRAM) to confirm BI-V100 hardware.
 2026-08-03 10:46:19 +00:00
dylanyunlon
8c1955dc92 fix: revert invalid patches, add honest tuning surface assessment 
REVERTED (invalid):
- paged_attn.py: restored use_v1=True hardcode. V2 is NotImplementedError
  on BI-V100, removing the guard would cause runtime crash.
- fused_moe.py: BLOCK_SIZE_N/K changes reverted. ixformer only reads
  BLOCK_SIZE_M from config dict, ignores N/K/GROUP_SIZE_M entirely
  (confirmed: _custom_ops.py:774 only passes config['BLOCK_SIZE_M']).
- _custom_ops.py: SMEM change reverted pending hardware confirmation.
- triton_flash_attention.py: autotune configs reverted (will re-add properly).
- prefix_prefill.py: comment enhancement reverted (was harmless but noisy).

ADDED:
- TUNING_SURFACE_TRUTH.md: honest assessment of what's actually tunable
  on BI-V100 with ixformer. Documents that bench_bi100.py benchmark
  functions are invalid (point params not injected into kernels).

Actual tuning surface is 5 parameters, not dozens:
  1. BLOCK_SIZE_M (fused_moe, passes to ixformer)
  2. use_v1 threshold (hardcoded True, V2 unimplemented)
  3. BLOCK/NUM_WARPS (prefix_prefill Triton JIT)
  4. SMEM declaration (affects Triton compiler)
  5. autotune config set (triton_flash_attention)
 2026-08-03 10:34:28 +00:00
dylanyunlon
dc9ac0a757 feat(muh): apply CCCL-derived BI-V100 tuning to 5 vllm Python files 
Applied via muh/vllm_bi100_patch.py --conservative:

1. paged_attn.py: removed use_v1=True hardcode, restored V1/V2 heuristic
   with BI-V100 threshold (16384 vs default 8192). SM=16 favors V1 longer.

2. fused_moe.py: BLOCK_SIZE_K 32→64 (better memory coalescing with 900GB/s
   BW), BLOCK_SIZE_N 32→64 for decode path. Qwen3.6 MoE: E≈128, topk=8.

3. _custom_ops.py: SMEM kept at 32KB (conservative mode, pending hardware
   confirmation). Added diagnostic comment.

4. prefix_prefill.py: enhanced BI-V100 block config comment with SMEM
   budget breakdown (BLOCK=64,N=64 → 48KB tight, N=32 → 32KB safe).

5. triton_flash_attention.py: added 2 BI-V100 autotune configs
   (64x32 and 32x64) for SM=16 occupancy characteristics.

CCCL basis: cub/benchmarks/bench/ %RANGE% parameter spaces (reduce 1044
combos, scan 5.4M, topk 1698, transform 25920) → SMEM pruning → policy
selector logic from tuning_*.cuh.

Also includes muh/vllm_bi100_patch.py (713 lines) for reproducible
one-shot patching with --dry-run, --conservative, and --revert modes.
 2026-08-03 10:27:10 +00:00
dylanyunlon
094c710efa feat(muh): add bench_bi100.py — CCCL BruteForceSeeker for BI-V100 
Translates NVIDIA CCCL benchmark infrastructure to Iluvatar hardware:
- Extracts ALL %RANGE% parameter spaces from 95 CUB benchmark .cu files
- SMEM constraint pruning: eliminates 25-63% of invalid combos
- 6 hot-path algorithms with validated space sizes:
  reduce=1044 scan=5.4M(pruned) topk=1698 transform=25920 for=566
- CCCL-compatible output format
- --prune-only works without GPU
- --update-schema writes best results back to muh/schema/*.yaml
- --smem-limit flag for 32KB vs 48KB investigation
 2026-08-03 10:24:37 +00:00
Claude
9f93d695a9 feat: deploy CCCL-tuned prefix_prefill + muh_dispatch + fix SM=16 count 
muh_dispatch.py:
- Fix missing os/sys imports (was crashing on import)
- Fix SM count 50→16 (confirmed via ixsmi, matches hardware.cuh)
- Fix C++ struct name lookup to match actual tuning_reduce.cuh names:
  bi100_plus_float32_o4, bi100_plus_float64_o4, bi100_plus_accum2_o4
  (was: bi100_float32_plus_o4 — wrong name, would always fall through to default)

Dockerfile:
- Add COPY for prefix_prefill.py and muh_dispatch.py
- Deploy CCCL-tuned prefix_prefill.py into vllm attention ops
  (BLOCK=64, NUM_WARPS=4 for BI-V100 SM=16)
- Deploy muh_dispatch.py into vllm package for type-dispatched kernel configs
- These files were written but never deployed — dead code until now

Impact: prefix_prefill.py deployment means the CCCL-derived block sizes
actually take effect at runtime. Previously the base image's original
prefix_prefill.py (BLOCK=128 for cc>=80, or 64 for cc<80) was used,
which is correct for BI-V100 but our version adds explicit SM=16
documentation and the path for future tuning.
 2026-08-03 08:30:16 +00:00
Claude
8e9c22f6c1 feat: CCCL-derived 3-tier decode dispatch + SM=16 prefill tuning + multi-step scheduling 
paged_attn.py:
- Remove use_v1=True hardcode that forced all decode through ixf_F V1
- Wire up paged_attention_v2_triton.py as Tier 2 decode path for seq_len > 8192
- 3-tier dispatch: V1 (short) → Triton V2 (long) → PyTorch (fallback)
- Triton V2 uses CCCL compound-reduce pattern (summary_statistics.cu)
  with GQA broadcast (6x KV read reduction for Qwen3.6)
- This is the single highest-impact change: Output TPS is 83% of score

prefix_prefill.py:
- CCCL scan-tuning-informed block sizes for BI-V100 (SM=16, 48KB SMEM)
- BI-V100 path: BLOCK=64 NUM_WARPS=4 (vs BLOCK=128 NUM_WARPS=8 on A100+)
- Matches muh/tuning/tuning_scan.cuh bi100_lookback_4B_o4 pattern
- Fewer warps = less register pressure = higher occupancy on 16 SMs

computility-run.yaml:
- Add --num-scheduler-steps=8: batch 8 decode iterations per Python call
  (cuts scheduler overhead ~8x, directly improves Output TPS)
- Add --preemption-mode=recompute (cheaper than swap on BI-V100 HBM)
- Add TRITON_CACHE_DIR for JIT warmup persistence
- Add TRITON_PRINT_AUTOTUNING=0 (use hardcoded CCCL configs, skip autotune)

Competition impact estimate:
- Tier 2 Triton V2 replaces PyTorch fallback for 8K-100K contexts → ~5-10x decode speedup
- Multi-step scheduling → ~20-30% Output TPS improvement
- SM=16 block tuning → ~10-15% Input TPS improvement
 2026-08-03 08:28:38 +00:00
Claude
16981f221e feat(muh): reduce_by_key 55→203 lines — full key_size×accum_size dispatch 
From 1KB/55 lines (46× compression vs CCCL 70KB) to 203 lines:
- Add 11 type specialization structs (key=1,2,4,8 × accum=1,2,4,8)
- SM=16 tile maximization: k4_a4 hot path 100% SMEM (256*24*8=49152)
- k8_a8 also at 100% SMEM (192*16*16=49152)
- Delay halved for L2=6MB across all branches
- CCCL-matching ReduceByKeyPolicy struct with ReduceByKeyAlgorithm enum
- Dynamic SMEM fallback for unknown pair sizes
 2026-08-03 07:20:23 +00:00
Claude
bdaec8da4b feat(muh): select_if SM=16 tile maximization 
- Increase tiles across all elem_size branches for SM=16 (fewer CTAs need larger tiles)
- Flagged path: items increased 20-80% (e.g. elem≤2: 18→24, elem≤4: 14→18)
- Non-flagged path: items increased 30-100% (e.g. elem≤4: 18→24, elem≤8: 14→16)
- Add SMEM utilization comments for each branch (target ≥50%)
- No structural change to 3-dimension dispatch (may_alias/flagged/delay)
 2026-08-03 07:19:13 +00:00
Claude
95d872e8f5 feat(muh): scan_by_key 53→284 lines — full key_size×val_size type dispatch 
From 1KB/53 lines (59× compression vs CCCL 85KB) to 284 lines:
- Add 16 type specialization structs (key_size=1,2,4,8 × val_size=1,2,4,8)
- SM=16 tile maximization: k4_v4 (attention hot path) 30720→49152 (62%→100% SMEM)
- SM=16 tile increases across all small pairs (k1_v1: 3072→12288, k2_v1: 6144→15360)
- Delay halved for L2=6MB: fixed_delay values /2 (less inter-CTA contention)
- Proper CCCL-matching ScanByKeyPolicy struct with ScanByKeyAlgorithm enum
- SMEM-safe fallback with dynamic items computation from pair_size
- Macro-based dispatch (MK_POLICY) for clean type selection
 2026-08-03 07:18:23 +00:00
Claude
88db0ed89c feat(muh): SM=16 tuning overhaul — reduce/scan/transform 
tuning_reduce.cuh (201→311 lines):
- Add accum_size=1/2/16 branches (int8, bfloat16, int128)
- Add min/max op dispatch (same params as plus for BI-V100)
- SM=16 tile maximization: det_float32 tile 11648→49152 (23%→100% SMEM)
- SM=16 tile maximization: det_float64 tile 11264→49152 (23%→100% SMEM)
- Add float32_o8, int64_o4/o8 variants with vec_size dispatch
- Increase float32 items 16→24 (32768→49152, fill SMEM for fewer CTAs)

tuning_scan.cuh:
- Fix 1B tile from 9216→16384 (19%→33% SMEM, scan needs 2x buffer)
- Fix 2B tile from 13312→24576 (27%→100% SMEM with double buffer)
- Fix 8B_o4 tile: threads 416→384 for warp alignment, items 14→16
- Update header comments with confirmed SM=16 hardware profile
- Document lookback delay heuristic for L2=6MB

tuning_transform.cuh (128→168 lines):
- CRITICAL: bytes_in_flight 16KB→32KB (was based on 900/50=18 GB/s,
  actual is 900/16=56 GB/s — 3× error)
- Add full PrefetchPolicy struct matching CCCL upstream
- Add AsyncCopyPolicy with BI-V100 fallback (no cp.async support)
- Document CCCL cc_to_min_bytes_in_flight reference values
- Add vec_size calculation from element size (16-byte vector loads)
- Cap items_per_thread at 32 to prevent register pressure

hardware.cuh:
- Add SMEM 48KB vs 32KB disambiguation note
 2026-08-03 07:16:35 +00:00
Claude
0ba4cdb025 fix: dial back max-num-seqs 256→8, revert batched-tokens and mem-util 
256 concurrent seqs risks OOM: worst case with long prompts in queue
can exhaust KV cache + activation memory. 32K batched-tokens prefill
activation ≈ 20GB competes with KV cache. 0.95 mem-util leaves only
5% headroom for spikes.

Conservative start: max-num-seqs=8 (8× improvement over baseline=1).
8 seqs × 2048 avg context × 80KB/token = 1.3GB KV cache, safe.
gpu-memory-utilization and max-num-batched-tokens restored to proven
baseline values.

Optimal max-num-seqs needs real-hardware sweep: 4→8→16→32→64→128.
The value where Output TPS plateaus (KV cache saturated) is the
answer. Can't determine this without Phanthy Cloud access.
 2026-08-03 06:51:33 +00:00
Claude
cdc01bbc6a fix: critical config + tuning corrections from CCCL source analysis 
computility-run.yaml:
  max-num-seqs 1→256: benchmark sweeps [128,256] concurrent seqs,
    current config processes 1 while 127 queue. KV cache budget:
    256 seqs × 2048 tokens × 80KB/token = 41.9GB < 45GB available.
  max-num-batched-tokens 8192→32768: support 256 concurrent prefills.
  gpu-memory-utilization 0.9→0.95: provide KV cache headroom.

Dockerfile:
  Deploy paged_attention_v2_triton.py to vllm package path so
  try-triton-first logic in _custom_ops.py can find it. Falls back
  to PyTorch V2 automatically if Triton V2 fails (SMEM/runtime).

muh/tuning/common.cuh:
  scale_mem_bound max_smem now a parameter (default 48KB). Allows
  policy_selectors to pass hw.max_shared_memory_per_block if actual
  SMEM differs from CCCL 48KB assumption.

muh/tuning/tuning_transform.cuh:
  bytes_in_flight 16KB→32KB. Old derivation used 900/50=18 GB/s/SM
  (wrong, SM=16 confirmed). Actual per-SM BW = 56 GB/s.
  32KB is estimate pending benchmark sweep.

SM count 50→16 corrections across all affected files.
 2026-08-03 06:45:54 +00:00
Claude
071fa361a3 docs: CCCL → Triton methodology transfer — parameter search translation table 
Maps CCCL %RANGE% benchmark format to EngineX Triton autotune configs:
- prefix_prefill: ipt→BLOCK_M, tpb→num_warps
- triton_flash_attention: 8 configs safety filter by SMEM
- fused_moe: BLOCK_SIZE_M/N/K grid search from CCCL transform/reduce
- Execution plan: hardware confirm → grid search → filter → deploy
- Competitive advantage: systematic search vs guessing
 2026-08-03 04:37:23 +00:00
Claude
e48a46a30d docs: EngineX vllm injection map — Python not C++, Triton not CUDA, 32KB SMEM claim 
CRITICAL FINDINGS from enginex-vllm-bi100-qwen36-main.zip analysis:
1. No .cu files — all CUDA kernels pre-compiled in ixf_F (ixformer.functions)
2. paged_attention_v2 is NotImplementedError, use_v1=True hardcoded
3. Real tuning surface: BLOCK/NUM_WARPS in Triton, BLOCK_SIZE_M/N/K in MoE
4. _custom_ops reports SMEM=32KB (not 48KB!) — needs hardware verification
5. muh strategy shifts from C++ injection to Python parameter optimization
6. CCCL methodology still applies but targets Triton kernels not CUB dispatch
 2026-08-03 03:59:49 +00:00
Claude
9bba7f4c79 docs: CCCL integration status — 462 assets inventory, 8/8 decode hot path coverage, no-clone-more verdict 
- Complete CCCL asset inventory: 52 Thrust examples + 18 CUB examples + 234 Catch2 tests + 78 benchmarks + 27+27 tuning headers
- Decode hot path matrix: reduce/scan/topk/radix_sort/transform/select_if/batch_memcpy/for all covered
- SM count=16 impact analysis on tuning parameters
- muh toolchain status: 27/27 headers, gen_patch/gen_yaml/parse all functional
- Verdict: 8,900 files already sufficient, remaining 31K files are cmake/CI scaffolding
- 信创魔盒定位: muh是算法因子置换层，不是连接器适配层
 2026-08-03 03:50:24 +00:00
Claude
392e644611 feat: add qwen3_5.py vllm adapter for Qwen3.6-35B-A3B 
588-line vllm model implementation based on qwen3_moe.py.
Bootstrap strategy: treat ALL layers as full attention (ignoring
linear_attention optimization). Correct but suboptimal.

Key adaptations:
- _get_text_config(): unwrap composite config -> text_config
- Shared expert support (shared_expert_intermediate_size)
- Skip linear attention weights (conv1d, delta_net, gated_delta)
- Skip vision encoder and MTP weights
- QK norm (Qwen3 style)
- Partial rotary embedding (rope_pct=0.25)

Includes deploy.sh and run_baseline.sh for server deployment.
 2026-08-01 13:54:33 +00:00
root
6beb497447 fix(hardware): SM count 50→16 confirmed on Phanthy Cloud BI-V100 
ixsmi + torch.cuda.get_device_properties confirmed:
- multi_processor_count: 16 (not 50 as in spec sheet)
- compute_capability: 7.0 (Volta-compatible)
- max_threads_per_SM: 8192
- total_memory: 32GB per GPU
- SM clock: 1500MHz (max 2500MHz)

Impact: bandwidth_per_sm = 900/16 = 56.25 GB/s (was 18 GB/s at 50 SM)
All occupancy and tile-size calculations need revision.
 2026-08-01 13:39:28 +00:00
Claude
fee8f1b9e4 docs: document Qwen3.6-35B-A3B bootstrap failure and architecture analysis 
vllm 0.6.3 KeyError on qwen3_5_moe model type.
Model is hybrid linear+full attention MoE with 256 experts (top-8).
enginex-vllm-bi100-qwen36-main.zip in repo likely contains the fix.
 2026-08-01 13:16:01 +00:00
Claude
9b0d1c283c docs: add competition server profile (4×BI-V100, Qwen3.6-35B-A3B) 
Hardware: 4× Iluvatar BI-V100 32GB, Xeon Gold 6530, 503GB RAM
Software: vllm 0.6.3+corex.3.2.3, torch 2.1.0+corex.3.2.3
Model: Qwen3.6-35B-A3B at /root/public-storage/models/Qwen/
Benchmark: benchmark_server_v0.5.0.py with automated sweeps
 2026-08-01 13:12:59 +00:00
dylanyunlon
79730ea907 test: add SMEM safety validator for all 26 tuning algorithms 
191 combinations tested: algorithm × type_size × (key,value) pairs.
Verifies every policy_selector output satisfies tile ≤ 49152 bytes.
Exit code 0 = all safe, 1 = overflow detected.

Usage: python3 muh/tests/test_smem_safety.py [--verbose]
 2026-08-01 12:37:14 +08:00
dylanyunlon
0154a3b297 fix(tuning_batched_topk): force bits=8, fix SMEM overflow 
Previous version used base topk policy's bits (11 for key>=2B),
causing SMEM overflow: 512*4*key_size + 2048*4*batches > 49152.

Fix: force bits=8 (same as radix_sort decision for BI-V100).
SMEM: 512*4*key_size + 256*4*batches = manageable.
Also adds while-loop SMEM check on max_batches.

Detected by test_smem_safety.py: 3 overflows at key_size=2,4,8.
 2026-08-01 12:36:57 +08:00
dylanyunlon
2c5e77f370 feat(gen_patch): add TUNING_REGISTRY for all 26 algorithms 
Registers all 26 CUB algorithms with metadata:
- 6 'injection' mode: have VLLM_INJECTION_POINTS (reduce/scan/topk/transform/batch_memcpy/for)
- 20 'library' mode: used via CCCL device API, no direct #define injection
- struct_mode: 'named' (bi100_* structs) vs 'inline' (policy_selector returns)

Also adds coverage reporting to generate_patches().
 2026-08-01 12:33:14 +08:00
dylanyunlon
84c18150e6 fix(tuning_select_if): restore 3 collapsed dispatch dimensions 
Previous version collapsed 77 CCCL specializations into 4 if/else
branches by elem_size only, losing:

1. may_alias dimension: now dispatches LOAD_CA (alias-safe) vs
   LOAD_DIRECT+LOAD_LDG (no-alias, ~5-10% faster for common case).
   CCCL SM100 no-alias small-type uses BLOCK_LOAD_DIRECT.

2. has_flags dimension: flagged path now gets 2-4 fewer items_per_thread
   because flag array takes additional SMEM. SMEM check includes flag_tile.

3. delay dimension: type-size-dependent delays instead of fixed(350,450).
   Scaled from CCCL SM100 benchmarks: ns*0.5, l2w*0.6 for BI-V100 L2.

SMEM check: input_tile + output_scatter + flag_tile ≤ 48KB.
 2026-08-01 02:26:48 +08:00
dylanyunlon
9287700964 fix(tuning_radix_sort): remove invented portioned_smem_per_warp field 
The previous version had a `portioned_smem_per_warp` field that doesn't
exist in CCCL. The actual CCCL RadixSortOnesweepPolicy has:
  threads, items, store_algorithm, rank_algorithm, scan_algorithm,
  rank_private_partitions, radix_bits

Also adds proper SMEM calculation:
  total = max(keys_tile, values_tile, rank_smem) + offsets
  with 2KB headroom for kernel stack/locals.

rank_private_partitions set to 1 to minimize SMEM pressure.
 2026-08-01 02:26:46 +08:00
dylanyunlon
2bc3263793 [muh] add tuning_radix_sort.cuh: BI-V100 tuning for radix_sort 
Translated from CCCL with SMEM overflow protection.
All SM100 values checked against 48KB limit.
 2026-08-01 02:11:05 +08:00
dylanyunlon
437fc3ea20 [muh] add tuning_unique_by_key.cuh: BI-V100 tuning for unique_by_key 
Translated from CCCL with SMEM overflow protection.
All SM100 values checked against 48KB limit.
 2026-08-01 02:11:03 +08:00
dylanyunlon
58de86d817 [muh] add tuning_select_if.cuh: BI-V100 tuning for select_if 
Translated from CCCL with SMEM overflow protection.
All SM100 values checked against 48KB limit.
 2026-08-01 02:11:01 +08:00
dylanyunlon
91f9a3a0e5 [muh] add tuning_scan_by_key.cuh: BI-V100 tuning for scan_by_key 
Translated from CCCL with SMEM overflow protection.
All SM100 values checked against 48KB limit.
 2026-08-01 02:10:59 +08:00
dylanyunlon
0ec355cf74 [muh] add tuning_reduce_by_key.cuh: BI-V100 tuning for reduce_by_key 
Translated from CCCL with SMEM overflow protection.
All SM100 values checked against 48KB limit.
 2026-08-01 02:10:57 +08:00
dylanyunlon
915c4aff56 [muh] add tuning_segmented_sort.cuh: BI-V100 tuning for segmented_sort 
Translated from CCCL with SMEM overflow protection.
All SM100 values checked against 48KB limit.
 2026-08-01 02:10:55 +08:00
dylanyunlon
561a82c849 [muh] add tuning_three_way_partition.cuh: BI-V100 tuning for three_way_partition 
Translated from CCCL with SMEM overflow protection.
All SM100 values checked against 48KB limit.
 2026-08-01 02:10:54 +08:00
dylanyunlon
aeb270578f [muh] add tuning_rle_non_trivial_runs.cuh: BI-V100 tuning for rle_non_trivial_runs 
Translated from CCCL with SMEM overflow protection.
All SM100 values checked against 48KB limit.
 2026-08-01 02:10:52 +08:00
dylanyunlon
f3ae28bbb5 [muh] add tuning_rle_encode.cuh: BI-V100 tuning for rle_encode 
Translated from CCCL with SMEM overflow protection.
All SM100 values checked against 48KB limit.
 2026-08-01 02:10:50 +08:00
dylanyunlon
f838c22bad [muh] add tuning_histogram.cuh: BI-V100 tuning for histogram 
Translated from CCCL with SMEM overflow protection.
All SM100 values checked against 48KB limit.
 2026-08-01 02:10:48 +08:00
dylanyunlon
3a8030224b [muh] add tuning_segmented_radix_sort.cuh: BI-V100 tuning header for segmented_radix_sort 
Translated from CCCL cub/device/dispatch/tuning/tuning_segmented_radix_sort.cuh.
Uses hardware_capability dispatch instead of compute_capability.
 2026-08-01 02:08:44 +08:00