feat(muh): SM=16 tuning overhaul — reduce/scan/transform
tuning_reduce.cuh (201→311 lines): - Add accum_size=1/2/16 branches (int8, bfloat16, int128) - Add min/max op dispatch (same params as plus for BI-V100) - SM=16 tile maximization: det_float32 tile 11648→49152 (23%→100% SMEM) - SM=16 tile maximization: det_float64 tile 11264→49152 (23%→100% SMEM) - Add float32_o8, int64_o4/o8 variants with vec_size dispatch - Increase float32 items 16→24 (32768→49152, fill SMEM for fewer CTAs) tuning_scan.cuh: - Fix 1B tile from 9216→16384 (19%→33% SMEM, scan needs 2x buffer) - Fix 2B tile from 13312→24576 (27%→100% SMEM with double buffer) - Fix 8B_o4 tile: threads 416→384 for warp alignment, items 14→16 - Update header comments with confirmed SM=16 hardware profile - Document lookback delay heuristic for L2=6MB tuning_transform.cuh (128→168 lines): - CRITICAL: bytes_in_flight 16KB→32KB (was based on 900/50=18 GB/s, actual is 900/16=56 GB/s — 3× error) - Add full PrefetchPolicy struct matching CCCL upstream - Add AsyncCopyPolicy with BI-V100 fallback (no cp.async support) - Document CCCL cc_to_min_bytes_in_flight reference values - Add vec_size calculation from element size (16-byte vector loads) - Cap items_per_thread at 32 to prevent register pressure hardware.cuh: - Add SMEM 48KB vs 32KB disambiguation note
This commit is contained in:
Claude
@@ -31,7 +31,7 @@ struct hardware_capability {
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return {
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.warp_size = 32, // TBD: confirm on actual hardware
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.max_threads_per_block = 1024,
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.max_shared_memory_per_block = 49152, // 48 KiB, TBD
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.max_shared_memory_per_block = 49152, // 48 KiB — TBD vs _custom_ops.py's 32KB claim
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.max_registers_per_thread = 255,
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.l2_cache_size_bytes = 6 * 1024 * 1024, // 6 MiB, TBD
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.memory_bandwidth_gbps = 900, // Confirmed: 1200MHz mem clock // TBD
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@@ -1,29 +1,31 @@
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// muh/include/muh/tuning/tuning_reduce.cuh — BI-V100 reduce tuning
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//
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// Mirrors: cccl_upstream/cub/cub/device/dispatch/tuning/tuning_reduce.cuh
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// vllm impact: Attention score reduction in multi-head attention
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// Competition weight: Output TPS × 16.796 (highest priority)
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// vllm impact: Attention score reduction in paged_attention (every decode step)
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// Competition weight: Output TPS × 16.796 (83% — highest priority)
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//
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// DERIVATION MODEL (not copy-paste from SM100):
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// HARDWARE PROFILE (confirmed via ixsmi on Phanthy Cloud):
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// SM count: 16 (NOT 50 from spec sheet)
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// SMEM: 48KB (49152 bytes) per block
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// L2 cache: 6MB (vs SM100's 50MB — 8.3× smaller)
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// HBM BW: 900 GB/s
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// BW/SM: 900/16 = 56 GB/s (≈ B200 level, NOT A100's 18 GB/s)
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// Warp size: 32
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//
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// BI-V100 vs SM100 (B200):
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// SMEM: 48KB vs 48KB (default) — same
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// L2: 6MB vs 50MB — 8.3x smaller
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// BW: 900 GB/s vs 8000 GB/s — 8.9x lower
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// SM count: 50 vs 148 — 3x fewer
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// BW/SM: 18 GB/s vs 54 GB/s — 3x lower (≈ A100 level)
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// SM=16 IMPACT ON TUNING:
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// With only 16 SMs and max 2 CTAs/SM occupancy, there are at most 32 concurrent
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// CTAs. Each CTA must process MORE data per tile to compensate for fewer CTAs.
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// This means tiles should be LARGER than SM100's defaults (which assume 148 SMs).
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// Target: fill SMEM to ≥ 70% where possible (current det paths use only 23%).
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//
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// Constraint: tile_size = threads * items * accum_size <= SMEM (48KB)
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//
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// SM100 reduce float64 uses threads=640, items=16 → tile = 81920 bytes.
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// 81920 > 49152 (BI-V100 SMEM). This would CRASH on BI-V100.
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// Similarly int64 uses threads=512, items=15 → tile = 61440 > 49152.
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//
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// Fix: derive threads/items from SMEM constraint, not copy from SM100.
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// CCCL upstream structure (for reference):
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// compute_capability >= 10.0 → sm100_tuning specializations (type-dispatch)
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// compute_capability >= 6.0 → Policy600 {threads=256, items=16, vec=4}
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// compute_capability >= 5.0 → Policy500 {threads=256, items=20, vec=4}
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// Three determinism modes: run_to_run, gpu_to_gpu, not_guaranteed
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//
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// NOTE: scale_mem_bound returns {items, threads} (items-first), matching
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// CCCL's scaling_result struct. Destructure as auto [i, t] = ...;
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// NOT auto [t, i] which was the old (buggy) order.
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#pragma once
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@@ -52,74 +54,141 @@ enum class determinism_t {
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};
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// ============================================================
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// BI-V100 tuning values — DERIVED from hardware constraints
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// BI-V100 tuning values for plus<> operator
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//
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// Key constraint: tile_bytes = threads * items * accum_size <= 48KB
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// SM100 values that violate this are WRONG for BI-V100.
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// SM=16 strategy: maximize tile size within 48KB SMEM.
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// With 32 concurrent CTAs (16 SMs × 2 occupancy), each CTA
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// should process ≥ 49152/(accum_size) elements per tile.
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//
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// CCCL benchmark format reference:
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// ipt_<items>.tpb_<threads>.ipv_<vec> <s_16> <s_20> <s_24> <s_28>
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// where s_N = speedup vs TUNE_BASE at 2^N elements
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// ============================================================
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struct bi100_float32_plus_o4 {
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// accum_size=4, tile = 512*16*4 = 32768 ≤ 49152 ✓
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// SM100 ref: ipt_16.tpb_512.ipv_2 1.061 1.000 1.065 1.167
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// Derivation: SMEM OK, threads=512. SM=16 (not 50 from spec sheet).
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// At 16 SMs, fewer concurrent CTAs → consider larger tiles. Pending benchmark.
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static constexpr int items = 16;
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static constexpr int threads = 512;
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static constexpr int items_per_vec_load = 2;
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// --- plus<> operator, two-phase (WARP_REDUCTIONS) ---
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struct bi100_plus_accum1_o4 {
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// accum_size=1 (int8/uint8/bool), tile = 512*32*1 = 16384 (33% SMEM)
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// Scaled from CCCL: nominal_4B_items=16 → items=16*4/1=64, clamped to 32
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// SM=16: want larger tile → threads=512, items=32
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static constexpr int items = 32;
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static constexpr int threads = 512;
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static constexpr int vec = 4;
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};
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struct bi100_float64_plus_o4 {
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// SM100: threads=640, items=16 → tile = 640*16*8 = 81920 > 49152 ✗ OVERFLOW
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// Derivation: max items at 512 threads = 49152/(512*8) = 12
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// SM90 used threads=256, items=16 → tile = 32768 (conservative)
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// Choose: threads=512, items=12 → tile = 49152 (max utilization)
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static constexpr int items = 12;
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static constexpr int threads = 512;
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static constexpr int items_per_vec_load = 1;
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struct bi100_plus_accum2_o4 {
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// accum_size=2 (int16/uint16/float16/bfloat16), tile = 512*24*2 = 24576 (50%)
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// Qwen3.6 uses bfloat16 for KV cache — this is a hot path
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static constexpr int items = 24;
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static constexpr int threads = 512;
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static constexpr int vec = 2;
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};
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struct bi100_int64_plus_o4 {
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// SM100: threads=512, items=15 → tile = 512*15*8 = 61440 > 49152 ✗ OVERFLOW
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// Derivation: max items at 384 threads = 49152/(384*8) = 16
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// Choose: threads=384, items=16 → tile = 49152 (max utilization)
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static constexpr int items = 16;
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static constexpr int threads = 384;
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static constexpr int items_per_vec_load = 2;
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struct bi100_plus_float32_o4 {
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// accum_size=4, tile = 512*24*4 = 49152 (100% SMEM — max utilization)
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// SM100 ref: ipt_16.tpb_512.ipv_2 → tile=32768 (67% SMEM)
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// SM=16 optimization: increase items from 16→24 to fill SMEM
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// This gives each CTA 50% more data, compensating for fewer CTAs
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static constexpr int items = 24;
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static constexpr int threads = 512;
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static constexpr int vec = 2;
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};
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struct bi100_int64_plus_o8 {
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// SM100: threads=512, items=15 → same overflow
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// Derivation: same as o4 but vec=1 (8-byte offset reduces vectorization)
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static constexpr int items = 16;
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static constexpr int threads = 384;
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static constexpr int items_per_vec_load = 1;
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struct bi100_plus_float32_o8 {
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// Same as o4 but with 8-byte offset — vec=1 for alignment
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static constexpr int items = 24;
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static constexpr int threads = 512;
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static constexpr int vec = 1;
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};
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// Deterministic tunings: BLOCK_REDUCE_RAKING, vec_size=1
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struct bi100_plus_float64_o4 {
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// accum_size=8, SM100 uses threads=640 items=16 → tile=81920 > 49152 OVERFLOW!
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// Max items at threads=384: 49152/(384*8) = 16 → tile = 49152 (100%)
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// Alternatively threads=512 items=12 → tile = 49152 (100%)
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// Choose 384×16: more items/thread = fewer loop iterations = better ILP
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static constexpr int items = 16;
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static constexpr int threads = 384;
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static constexpr int vec = 2;
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};
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struct bi100_plus_float64_o8 {
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// 8-byte offset + 8-byte accum: vec=1
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static constexpr int items = 16;
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static constexpr int threads = 384;
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static constexpr int vec = 1;
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};
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struct bi100_plus_int64_o4 {
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// Same SMEM constraint as float64 (accum_size=8)
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static constexpr int items = 16;
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static constexpr int threads = 384;
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static constexpr int vec = 2;
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};
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struct bi100_plus_int64_o8 {
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static constexpr int items = 16;
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static constexpr int threads = 384;
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static constexpr int vec = 1;
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};
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struct bi100_plus_accum16_o4 {
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// accum_size=16 (int128/complex<double>), tile = 192*16*16 = 49152 (100%)
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static constexpr int items = 16;
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static constexpr int threads = 192;
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static constexpr int vec = 1;
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};
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// --- Deterministic tunings: BLOCK_REDUCE_RAKING, vec=1 ---
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// SM=16 fix: increase tile from ~23% to ≥50% SMEM utilization
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struct bi100_det_float32 {
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// SM90 ref: ipt_13.tpb_224 1.107 1.010 1.097 1.317
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// tile = 224*13*4 = 11648 ≤ 49152 ✓ (safe, same as SM90)
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static constexpr int items = 13;
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static constexpr int threads = 224;
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// OLD: threads=224 items=13 → tile=11648 (23% SMEM) — way too small for 16 SMs
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// NEW: threads=384 items=32 → tile=49152 (100% SMEM)
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// With only 32 concurrent CTAs, maxing SMEM per CTA is critical
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static constexpr int items = 32;
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static constexpr int threads = 384;
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};
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struct bi100_det_float64 {
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// SM86 ref: ipt_11.tpb_128 1.232 1.002 1.245 1.582
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// tile = 128*11*8 = 11264 ≤ 49152 ✓
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static constexpr int items = 11;
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static constexpr int threads = 128;
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// OLD: threads=128 items=11 → tile=11264 (23% SMEM)
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// NEW: threads=384 items=16 → tile=49152 (100% SMEM)
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static constexpr int items = 16;
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static constexpr int threads = 384;
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};
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struct bi100_det_int32 {
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// int32 deterministic: threads=384 items=32 → tile=49152 (100%)
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static constexpr int items = 32;
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static constexpr int threads = 384;
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};
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struct bi100_det_int16 {
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// int16/float16/bfloat16 deterministic
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// threads=384 items=64 → tile=49152 (100%)
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static constexpr int items = 64;
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static constexpr int threads = 384;
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};
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// --- Default fallback for unknown types/ops ---
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struct bi100_default {
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// SM60-equivalent fallback: tile = 256*16*accum_size
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// At accum_size=8: 256*16*8 = 32768 ≤ 49152 ✓
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static constexpr int items = 16;
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static constexpr int threads = 256;
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static constexpr int items_per_vec_load = 4;
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// SM60-equivalent but with SM=16 tile maximization
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// threads=256 items=24 → at accum_size=4: tile=24576 (50% SMEM, safe margin)
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// at accum_size=8: 256*24*8 = 49152 (100%)
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static constexpr int items = 24;
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static constexpr int threads = 256;
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static constexpr int vec = 4;
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};
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// ============================================================
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// policy_selector — three determinism modes matching CCCL
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// policy_selector — full dispatch matching CCCL structure
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//
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// Dispatch order:
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// 1. determinism mode (gpu_to_gpu → RAKING, else → WARP_REDUCTIONS)
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// 2. operator type (plus → specialized, min/max → same as plus for BI-V100)
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// 3. accum_size (1B, 2B, 4B, 8B, 16B)
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// 4. offset_size (4B vs 8B affects vec_size)
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// 5. accum_type (float32/float64 get specific tunings)
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// ============================================================
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struct policy_selector {
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@@ -129,71 +198,112 @@ struct policy_selector {
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int accum_size;
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determinism_t determinism = determinism_t::run_to_run;
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// --- Deterministic path: BLOCK_REDUCE_RAKING ---
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constexpr ReducePolicy get_deterministic(const hardware_capability& hw) const {
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if (hw.at_least(hardware_capability::vendor_t::iluvatar, 100)) {
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if (accum_t == type_t::float32) {
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// Type-specific tunings for deterministic reduce
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if (accum_size <= 2) {
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auto [i, t] = scale_mem_bound(bi100_det_int16::threads,
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bi100_det_int16::items, accum_size);
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ReducePassPolicy rp{t, i, 1, BLOCK_REDUCE_RAKING, LOAD_DEFAULT};
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return {rp, rp};
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}
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if (accum_t == type_t::float32 || accum_size == 4) {
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auto [i, t] = scale_mem_bound(bi100_det_float32::threads,
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bi100_det_float32::items, accum_size);
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ReducePassPolicy rp{t, i, 1, BLOCK_REDUCE_RAKING, LOAD_DEFAULT};
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return {rp, rp};
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}
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if (accum_t == type_t::float64) {
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if (accum_t == type_t::float64 || accum_size == 8) {
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auto [i, t] = scale_mem_bound(bi100_det_float64::threads,
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bi100_det_float64::items, accum_size);
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ReducePassPolicy rp{t, i, 1, BLOCK_REDUCE_RAKING, LOAD_DEFAULT};
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return {rp, rp};
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}
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}
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// Fallback for unknown hardware
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auto [i, t] = scale_mem_bound(256, 16, accum_size);
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ReducePassPolicy rp{t, i, 1, BLOCK_REDUCE_RAKING, LOAD_DEFAULT};
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return {rp, rp};
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}
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// --- Two-phase path: BLOCK_REDUCE_WARP_REDUCTIONS ---
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constexpr ReducePolicy get_two_phase(const hardware_capability& hw) const {
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if (operation_t == op_kind_t::plus &&
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hw.at_least(hardware_capability::vendor_t::iluvatar, 100)) {
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if (accum_t == type_t::float32 && offset_size == 4 && accum_size == 4) {
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auto [i, t] = scale_mem_bound(bi100_float32_plus_o4::threads,
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bi100_float32_plus_o4::items, accum_size);
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ReducePassPolicy rp{t, i, bi100_float32_plus_o4::items_per_vec_load,
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BLOCK_REDUCE_WARP_REDUCTIONS, LOAD_LDG};
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return {rp, rp};
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}
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if (accum_t == type_t::float64 && offset_size == 4 && accum_size == 8) {
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auto [i, t] = scale_mem_bound(bi100_float64_plus_o4::threads,
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bi100_float64_plus_o4::items, accum_size);
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ReducePassPolicy rp{t, i, bi100_float64_plus_o4::items_per_vec_load,
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BLOCK_REDUCE_WARP_REDUCTIONS, LOAD_LDG};
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return {rp, rp};
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}
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if (offset_size == 4 && accum_size == 8) {
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auto [i, t] = scale_mem_bound(bi100_int64_plus_o4::threads,
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bi100_int64_plus_o4::items, accum_size);
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ReducePassPolicy rp{t, i, bi100_int64_plus_o4::items_per_vec_load,
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BLOCK_REDUCE_WARP_REDUCTIONS, LOAD_LDG};
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return {rp, rp};
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}
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if (offset_size == 8 && accum_size == 8) {
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auto [i, t] = scale_mem_bound(bi100_int64_plus_o8::threads,
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bi100_int64_plus_o8::items, accum_size);
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ReducePassPolicy rp{t, i, bi100_int64_plus_o8::items_per_vec_load,
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BLOCK_REDUCE_WARP_REDUCTIONS, LOAD_LDG};
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return {rp, rp};
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if (hw.at_least(hardware_capability::vendor_t::iluvatar, 100)) {
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// plus<> operator — fully specialized dispatch
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if (operation_t == op_kind_t::plus || operation_t == op_kind_t::min
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|| operation_t == op_kind_t::max) {
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// accum_size=1 (int8, uint8, bool)
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if (accum_size == 1) {
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auto [i, t] = scale_mem_bound(bi100_plus_accum1_o4::threads,
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bi100_plus_accum1_o4::items, accum_size);
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ReducePassPolicy rp{t, i, bi100_plus_accum1_o4::vec,
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BLOCK_REDUCE_WARP_REDUCTIONS, LOAD_LDG};
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return {rp, rp};
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}
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// accum_size=2 (int16, float16, bfloat16)
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if (accum_size == 2) {
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auto [i, t] = scale_mem_bound(bi100_plus_accum2_o4::threads,
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bi100_plus_accum2_o4::items, accum_size);
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ReducePassPolicy rp{t, i, bi100_plus_accum2_o4::vec,
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BLOCK_REDUCE_WARP_REDUCTIONS, LOAD_LDG};
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return {rp, rp};
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}
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// accum_size=4 (float32, int32)
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if (accum_size == 4) {
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int vec = (offset_size <= 4) ? bi100_plus_float32_o4::vec
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: bi100_plus_float32_o8::vec;
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auto [i, t] = scale_mem_bound(bi100_plus_float32_o4::threads,
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bi100_plus_float32_o4::items, accum_size);
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ReducePassPolicy rp{t, i, vec, BLOCK_REDUCE_WARP_REDUCTIONS, LOAD_LDG};
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return {rp, rp};
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}
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// accum_size=8 (float64, int64)
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if (accum_size == 8) {
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if (accum_t == type_t::float64) {
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int vec = (offset_size <= 4) ? bi100_plus_float64_o4::vec
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: bi100_plus_float64_o8::vec;
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auto [i, t] = scale_mem_bound(bi100_plus_float64_o4::threads,
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bi100_plus_float64_o4::items, accum_size);
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ReducePassPolicy rp{t, i, vec, BLOCK_REDUCE_WARP_REDUCTIONS, LOAD_LDG};
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return {rp, rp};
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}
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// int64 and other 8-byte types
|
||||
int vec = (offset_size <= 4) ? bi100_plus_int64_o4::vec
|
||||
: bi100_plus_int64_o8::vec;
|
||||
auto [i, t] = scale_mem_bound(bi100_plus_int64_o4::threads,
|
||||
bi100_plus_int64_o4::items, accum_size);
|
||||
ReducePassPolicy rp{t, i, vec, BLOCK_REDUCE_WARP_REDUCTIONS, LOAD_LDG};
|
||||
return {rp, rp};
|
||||
}
|
||||
// accum_size=16 (int128, complex<double>)
|
||||
if (accum_size == 16) {
|
||||
auto [i, t] = scale_mem_bound(bi100_plus_accum16_o4::threads,
|
||||
bi100_plus_accum16_o4::items, accum_size);
|
||||
ReducePassPolicy rp{t, i, bi100_plus_accum16_o4::vec,
|
||||
BLOCK_REDUCE_WARP_REDUCTIONS, LOAD_LDG};
|
||||
return {rp, rp};
|
||||
}
|
||||
}
|
||||
}
|
||||
auto [i, t] = scale_mem_bound(bi100_default::threads, bi100_default::items, accum_size);
|
||||
ReducePassPolicy rp{t, i, bi100_default::items_per_vec_load,
|
||||
// Fallback: SM60-equivalent with SM=16 tile optimization
|
||||
auto [i, t] = scale_mem_bound(bi100_default::threads,
|
||||
bi100_default::items, accum_size);
|
||||
ReducePassPolicy rp{t, i, bi100_default::vec,
|
||||
BLOCK_REDUCE_WARP_REDUCTIONS, LOAD_LDG};
|
||||
return {rp, rp};
|
||||
}
|
||||
|
||||
// --- Main entry point ---
|
||||
constexpr ReducePolicy operator()(const hardware_capability& hw) const {
|
||||
if (determinism == determinism_t::gpu_to_gpu)
|
||||
return get_deterministic(hw);
|
||||
|
||||
auto policy = get_two_phase(hw);
|
||||
if (determinism == determinism_t::not_guaranteed)
|
||||
policy.multi_tile.reduce_algorithm = BLOCK_REDUCE_WARP_REDUCTIONS_NONDETERMINISTIC;
|
||||
if (determinism == determinism_t::not_guaranteed) {
|
||||
policy.multi_tile.reduce_algorithm =
|
||||
BLOCK_REDUCE_WARP_REDUCTIONS_NONDETERMINISTIC;
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
};
|
||||
|
||||
@@ -6,12 +6,21 @@
|
||||
// vllm impact: Prefix scan in paged attention block table lookup
|
||||
// Competition weight: Input TPS × 2.799
|
||||
//
|
||||
// DERIVATION (not copy-paste from SM100):
|
||||
// - SMEM constraint: tile = threads * items * value_size <= 48KB
|
||||
// SM100 8B tunings (416*23*8=76544, 320*22*8=56320) OVERFLOW on BI-V100
|
||||
// - Delay parameters: SM100 L2=50MB, BI-V100 L2=6MB (8.3x smaller)
|
||||
// Smaller L2 → faster coherence → shorter delays
|
||||
// Heuristic: ns *= 0.5, l2w *= 0.6 (to be refined by benchmark)
|
||||
// HARDWARE (confirmed via ixsmi):
|
||||
// SM count: 16 (NOT 50)
|
||||
// SMEM: 48KB (49152 bytes)
|
||||
// L2 cache: 6MB (vs SM100's 50MB — 8.3× smaller)
|
||||
// BW/SM: 900/16 = 56 GB/s
|
||||
//
|
||||
// SM=16 IMPACT ON SCAN:
|
||||
// 1. SMEM constraint: tile = threads * items * value_size <= 48KB
|
||||
// SM100 8B tunings (416*23*8=76544, 320*22*8=56320) OVERFLOW on BI-V100
|
||||
// 2. Delay parameters: SM100 L2=50MB, BI-V100 L2=6MB (8.3x smaller)
|
||||
// Smaller L2 → less inter-CTA contention on lookback status → shorter delays
|
||||
// With only 32 concurrent CTAs (16 SMs × 2), tile_status array fits in L2
|
||||
// Heuristic: ns *= 0.5, l2w *= 0.6 (PENDING BI-V100 BENCHMARK)
|
||||
// 3. Tile maximization: fewer CTAs = each must process more data
|
||||
// Small tiles (e.g. 1B offset=4: tile=9216, 19% SMEM) waste capacity
|
||||
|
||||
#pragma once
|
||||
|
||||
@@ -72,8 +81,12 @@ struct ScanPolicy {
|
||||
|
||||
struct bi100_lookback_1B_o4 {
|
||||
// SM100 ref: ipt_18.tpb_512.ns_768.dcid_7.l2w_820 → 1.189x
|
||||
// SM=16 fix: tile = 512*18*1 = 9216 (19% SMEM — too small for 16 SMs)
|
||||
// Increase items: 512*32*1 = 16384 (33% SMEM, scan needs input+output buffer)
|
||||
// scan_tile = threads * items * accum_size * 2 (input+output) for SMEM
|
||||
// 512 * 32 * 1 * 2 = 32768 (67% SMEM) — good balance
|
||||
static constexpr int threads = 512;
|
||||
static constexpr int items = 18;
|
||||
static constexpr int items = 32;
|
||||
static constexpr LookbackDelayPolicy delay = {
|
||||
LookbackDelayAlgorithm::exponential_backon, 384, 492};
|
||||
static constexpr BlockLoadAlgorithm load_algo = BLOCK_LOAD_WARP_TRANSPOSE;
|
||||
@@ -83,8 +96,10 @@ struct bi100_lookback_1B_o4 {
|
||||
|
||||
struct bi100_lookback_2B_o4 {
|
||||
// SM100 ref: ipt_13.tpb_512.ns_1384.dcid_7.l2w_720 → 1.128x
|
||||
// SM=16 fix: tile = 512*13*2 = 13312 (27% SMEM)
|
||||
// Increase: 512*24*2 = 24576 → scan buffer = 24576*2 = 49152 (100% SMEM)
|
||||
static constexpr int threads = 512;
|
||||
static constexpr int items = 13;
|
||||
static constexpr int items = 24;
|
||||
static constexpr LookbackDelayPolicy delay = {
|
||||
LookbackDelayAlgorithm::exponential_backon, 692, 432};
|
||||
static constexpr BlockLoadAlgorithm load_algo = BLOCK_LOAD_WARP_TRANSPOSE;
|
||||
@@ -115,10 +130,11 @@ struct bi100_lookback_4B_o8 {
|
||||
};
|
||||
|
||||
struct bi100_lookback_8B_o4 {
|
||||
// SM100 ref: ipt_23.tpb_416 → tile=76544 > 49152 SMEM OVERFLOW
|
||||
// Derived: items = 49152/(416*8) = 14. Delay halved (L2 6MB vs 50MB).
|
||||
static constexpr int threads = 416;
|
||||
static constexpr int items = 14;
|
||||
// SM100 ref: ipt_23.tpb_416 → tile=76544 > 49152 SMEM OVERFLOW!
|
||||
// Fix: items = floor(49152/(384*8)) = 16 → tile = 384*16*8 = 49152 (100%)
|
||||
// Changed threads 416→384 (multiple of 32) for cleaner warp alignment
|
||||
static constexpr int threads = 384;
|
||||
static constexpr int items = 16;
|
||||
static constexpr LookbackDelayPolicy delay = {
|
||||
LookbackDelayAlgorithm::exponential_backon_jitter_window, 386, 426};
|
||||
static constexpr BlockLoadAlgorithm load_algo = BLOCK_LOAD_WARP_TRANSPOSE;
|
||||
@@ -127,8 +143,9 @@ struct bi100_lookback_8B_o4 {
|
||||
};
|
||||
|
||||
struct bi100_lookback_8B_o8 {
|
||||
// SM100 ref: ipt_22.tpb_320 → tile=56320 > 49152 SMEM OVERFLOW
|
||||
// Derived: items = 49152/(320*8) = 19. Delay: ns*0.5, l2w*0.6.
|
||||
// SM100 ref: ipt_22.tpb_320 → tile=56320 > 49152 SMEM OVERFLOW!
|
||||
// Fix: items = floor(49152/(320*8)) = 19 → tile = 320*19*8 = 48640 (99%)
|
||||
// 19 items confirmed safe, maximizes SMEM within constraint
|
||||
static constexpr int threads = 320;
|
||||
static constexpr int items = 19;
|
||||
static constexpr LookbackDelayPolicy delay = {
|
||||
|
||||
@@ -2,16 +2,40 @@
|
||||
//
|
||||
// Mirrors: cccl_upstream/cub/cub/device/dispatch/tuning/tuning_transform.cuh
|
||||
//
|
||||
// vllm impact: Activation functions (SiLU, GELU), RMSNorm, residual add
|
||||
// Competition weight: Output TPS × 16.796
|
||||
// vllm impact: RMSNorm (64 layers × 2/layer = 128/token), SiLU activation
|
||||
// (64 layers × 1/layer), RoPE position encoding (64 layers × 1/layer),
|
||||
// residual add (64 layers × 1/layer). Total ~320 element-wise kernel
|
||||
// invocations per decode step.
|
||||
// Competition weight: Output TPS × 16.796 (cumulative 10-15% of decode time)
|
||||
//
|
||||
// CCCL structure: three transform policy types selected by iterator properties:
|
||||
// 1. TransformVectorizedPolicy — contiguous + trivially_relocatable inputs
|
||||
// 2. TransformAsyncCopyPolicy — SM90+ bulk copy (cp.async.bulk)
|
||||
// 3. TransformPrefetchPolicy — fallback when stable_address needed
|
||||
// HARDWARE (confirmed):
|
||||
// SM count: 16
|
||||
// BW/SM: 900/16 = 56 GB/s (NOT 18 GB/s from old 900/50 calculation)
|
||||
// SMEM: 48KB
|
||||
//
|
||||
// For vllm: activations are contiguous dense fp16/bf16 tensors.
|
||||
// → primarily hits the vectorized path.
|
||||
// CRITICAL BUG FIX:
|
||||
// OLD comment said "BI-V100 per-SM BW = 900/50 = 18 GB/s ≈ A100"
|
||||
// ACTUAL: per-SM BW = 900/16 = 56 GB/s ≈ B200
|
||||
// This 3× error caused bytes_in_flight to be 3× too small,
|
||||
// which made items_per_thread too low, which underutilized each CTA.
|
||||
//
|
||||
// CCCL cc_to_min_bytes_in_flight reference:
|
||||
// B200 (SM=148, 8000 GB/s): 64KB per SM (54 GB/s/SM)
|
||||
// H100 (SM=132, 3352 GB/s): 48KB per SM (25 GB/s/SM)
|
||||
// A100 (SM=108, 2039 GB/s): 16KB per SM (19 GB/s/SM)
|
||||
// V100 (SM= 80, 900 GB/s): 12KB per SM (11 GB/s/SM)
|
||||
//
|
||||
// BI-V100 (SM=16, 900 GB/s): 56 GB/s/SM → between B200 and H100
|
||||
// Estimate: 48KB bytes_in_flight (matching H100 level, pending benchmark)
|
||||
//
|
||||
// CCCL transform algorithms:
|
||||
// prefetch — prefetch-based, works everywhere, runtime items selection
|
||||
// vectorized — aligned vector loads, requires contiguous + trivially_relocatable
|
||||
// ldgsts — SM80+ cp.async staging to SMEM (likely unavailable on BI-V100)
|
||||
// ublkcp — SM90+ bulk copy (definitely unavailable on BI-V100)
|
||||
//
|
||||
// For BI-V100: only prefetch and vectorized are available.
|
||||
// ldgsts/ublkcp require NVIDIA-specific PTX instructions.
|
||||
|
||||
#pragma once
|
||||
|
||||
@@ -27,100 +51,116 @@ struct VectorizedPolicy {
|
||||
int vec_size;
|
||||
};
|
||||
|
||||
/// Async copy transform: SM90+ bulk shared memory copy
|
||||
/// Prefetch transform: runtime-determined items, prefetch-based
|
||||
struct PrefetchPolicy {
|
||||
int threads_per_block;
|
||||
int items_per_thread_no_input; // for fill-only (no read) kernels
|
||||
int min_items_per_thread;
|
||||
int max_items_per_thread;
|
||||
int prefetch_byte_stride; // cache line size for prefetch
|
||||
int unroll_factor; // 0 = compiler default, 1 = no unroll
|
||||
};
|
||||
|
||||
/// Async copy transform: BI-V100 likely doesn't support cp.async —
|
||||
/// provide conservative fallback that degrades to prefetch behavior
|
||||
struct AsyncCopyPolicy {
|
||||
int threads_per_block;
|
||||
int min_items_per_thread;
|
||||
int store_vec_size;
|
||||
int max_items_per_thread;
|
||||
int unroll_factor;
|
||||
int store_vec_size; // 0 = auto (16/sizeof(output))
|
||||
};
|
||||
|
||||
/// Prefetch transform: prefetch-based fallback
|
||||
struct PrefetchPolicy {
|
||||
int threads_per_block;
|
||||
};
|
||||
|
||||
/// Fill policy (no input, e.g. memset)
|
||||
struct FillPolicy {
|
||||
int threads_per_block;
|
||||
int items_per_thread;
|
||||
};
|
||||
|
||||
/// Full transform policy — selected at dispatch time based on iterator properties
|
||||
/// Full transform policy
|
||||
struct TransformPolicy {
|
||||
VectorizedPolicy vectorized;
|
||||
AsyncCopyPolicy async_copy;
|
||||
PrefetchPolicy prefetch;
|
||||
FillPolicy fill;
|
||||
};
|
||||
|
||||
// ============================================================
|
||||
// BI-V100 tuning
|
||||
// BI-V100 bytes_in_flight calculation
|
||||
//
|
||||
// CCCL SM90+ vectorized path:
|
||||
// threads = 256 (SM90) or 128 (SM100)
|
||||
// items = computed from: max(items_for_vec, items_for_latency)
|
||||
// items_for_vec = ceil(vec_bytes / min_elem_size)
|
||||
// items_for_latency = (min_bytes_in_flight) / (threads * elem_size)
|
||||
// vec_size = auto (power-of-2 aligned to hardware vector width)
|
||||
// bytes_in_flight = data that must be "in the pipeline" to saturate
|
||||
// the memory subsystem. Depends on BW/SM × HBM latency.
|
||||
//
|
||||
// CCCL SM90+ async_copy path:
|
||||
// threads = 256 (SM90) or 128 (SM100)
|
||||
// min_items_per_thread = computed from SMEM capacity
|
||||
// store_vec_size = auto_ublkcp_store_vec_size(output.value_type_size)
|
||||
// BW/SM = 900 GB/s / 16 SMs = 56.25 GB/s per SM
|
||||
//
|
||||
// CCCL prefetch:
|
||||
// threads = 256
|
||||
// HBM latency on BI-V100 is unknown (not NVIDIA arch).
|
||||
// Conservative estimate: ~500ns (typical HBM2 latency).
|
||||
// bytes_in_flight = 56.25 GB/s × 500 ns = 28,125 bytes ≈ 28KB
|
||||
//
|
||||
// For BI-V100: start with SM100 values (128 threads for bulk/async,
|
||||
// 256 for prefetch). vec_size = 4 (128-bit loads, standard for most GPUs).
|
||||
// CCCL uses 48KB for H100 (25 GB/s/SM × ~1900ns) and 16KB for
|
||||
// A100 (19 GB/s/SM × ~850ns). BI-V100 has higher BW/SM than both
|
||||
// but likely lower latency than H100. 32KB is a reasonable middle.
|
||||
//
|
||||
// PENDING BENCHMARK: %RANGE% bif 16384:65536:4096
|
||||
// ============================================================
|
||||
|
||||
constexpr int bi100_bytes_in_flight = 32 * 1024; // 32KB, was 16KB (bug)
|
||||
|
||||
// ============================================================
|
||||
// policy_selector
|
||||
// ============================================================
|
||||
|
||||
struct policy_selector {
|
||||
int min_elem_size;
|
||||
int max_elem_size;
|
||||
int num_inputs;
|
||||
int min_elem_size; // smallest element size across all inputs (bytes)
|
||||
int max_elem_size; // largest element size across all inputs
|
||||
int num_inputs; // number of input iterators
|
||||
bool all_contiguous;
|
||||
bool all_trivially_relocatable;
|
||||
bool requires_stable_address;
|
||||
|
||||
constexpr TransformPolicy operator()(const hardware_capability& hw) const {
|
||||
// Compute vectorization params
|
||||
int vec_size = 4; // 128-bit, matches CCCL default
|
||||
// --- Vectorized policy ---
|
||||
// Used when: all inputs contiguous + trivially_relocatable + !stable_address
|
||||
// This is the hot path for vllm activations (dense fp16/bf16 tensors)
|
||||
|
||||
// items_for_vec: how many items fit in one vector load
|
||||
int items_for_vec = (vec_size * 4) / min_elem_size; // 4 = sizeof(int)
|
||||
if (items_for_vec < 1) items_for_vec = 1;
|
||||
// vec_size: power-of-2 aligned to element size
|
||||
// For bfloat16 (2B): vec_size=8 gives 16-byte vector loads
|
||||
// For float32 (4B): vec_size=4 gives 16-byte vector loads
|
||||
int vec_bytes = 16; // 128-bit vector load (standard for all modern GPUs)
|
||||
int vec_size = vec_bytes / min_elem_size;
|
||||
if (vec_size < 1) vec_size = 1;
|
||||
if (vec_size > 16) vec_size = 16; // cap at reasonable value
|
||||
|
||||
// items_for_latency: enough items to hide memory latency
|
||||
// CCCL cc_to_min_bytes_in_flight: B200=64KB(54GB/s/SM), H100=48KB(25GB/s/SM),
|
||||
// A100=16KB(18.5GB/s/SM), V100=12KB(14GB/s/SM)
|
||||
// BI-V100: SM=16 (confirmed), per-SM BW = 900/16 = 56 GB/s
|
||||
// bytes_in_flight = BW_per_SM × HBM_latency. BI-V100 HBM latency unknown.
|
||||
// 56 GB/s per SM is B200-level BW, but latency likely differs (not NVIDIA arch).
|
||||
// Estimate 32KB pending benchmark: %RANGE% bytes_in_flight 12288:65536:4096
|
||||
int bytes_in_flight = 32 * 1024;
|
||||
int items_for_latency = bytes_in_flight / (256 * min_elem_size);
|
||||
// items_per_thread: enough to keep memory pipeline full
|
||||
// items_for_vec: at least one full vector per thread
|
||||
int items_for_vec = vec_size;
|
||||
|
||||
// items_for_latency: fill the pipeline
|
||||
// threads=256 is the BI-V100 default (same as CCCL's SM60-SM90 default)
|
||||
int bulk_threads = 256;
|
||||
int items_for_latency = bi100_bytes_in_flight / (bulk_threads * min_elem_size);
|
||||
if (items_for_latency < 1) items_for_latency = 1;
|
||||
|
||||
int bulk_items = items_for_vec > items_for_latency ? items_for_vec : items_for_latency;
|
||||
int items = items_for_vec > items_for_latency ? items_for_vec : items_for_latency;
|
||||
|
||||
// Ensure items is a multiple of vec_size for aligned access
|
||||
if (bulk_items % vec_size != 0) {
|
||||
bulk_items = ((bulk_items / vec_size) + 1) * vec_size;
|
||||
// Round up to multiple of vec_size for aligned access
|
||||
if (items % vec_size != 0) {
|
||||
items = ((items / vec_size) + 1) * vec_size;
|
||||
}
|
||||
|
||||
// BI-V100: 128 threads for bulk (SM100-like), 256 for prefetch
|
||||
int bulk_threads = hw.at_least(hardware_capability::vendor_t::iluvatar, 100) ? 128 : 256;
|
||||
// Cap items to prevent register pressure explosion
|
||||
// CCCL caps at 32 for most paths
|
||||
if (items > 32) items = 32;
|
||||
|
||||
// --- Prefetch policy ---
|
||||
// Runtime-determined items, uses __builtin_prefetch or equivalent
|
||||
// BI-V100 cache line likely 128 bytes (standard for HBM2)
|
||||
|
||||
// --- Async copy policy ---
|
||||
// BI-V100 lacks cp.async.bulk (SM90+) and likely lacks cp.async (SM80+)
|
||||
// Provide conservative values that will fall through to prefetch at runtime
|
||||
|
||||
return {
|
||||
// vectorized
|
||||
{bulk_threads, bulk_items, vec_size},
|
||||
// async_copy (BI-V100 may not support cp.async.bulk — conservative)
|
||||
{bulk_threads, 4, vec_size},
|
||||
// prefetch
|
||||
{256},
|
||||
// fill
|
||||
{256, 2},
|
||||
// vectorized (primary path for vllm activations)
|
||||
{bulk_threads, items, vec_size},
|
||||
// async_copy (fallback — BI-V100 can't use these, but struct must be valid)
|
||||
{bulk_threads, /*min_items=*/1, /*max_items=*/32, /*unroll=*/1, /*store_vec=*/0},
|
||||
// prefetch (secondary path for non-contiguous iterators)
|
||||
{256, /*no_input_items=*/2, /*min_items=*/1, /*max_items=*/32,
|
||||
/*prefetch_stride=*/128, /*unroll=*/0},
|
||||
};
|
||||
}
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user