dylanyunlong/project_6

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dylanyunlon 6a56649d9a [muh] radix_sort 6%→19%, rle_encode 8%→21%, rle_non_trivial_runs 6%→18%: 完整移植 CCCL SM90/SM100 tuning tables + BI-V100 SMEM 48KB 约束

radix_sort.cuh (148→461 lines):
- 完整 get_sm90_tuning() + get_sm100_tuning() 含 benchmark annotations
- bi100_smem_cap() SMEM 48KB 约束 + reg_scale_onesweep()
- policy_selector: onesweep(key>=4B) / multi_pass(key<4B)

rle_encode.cuh (54→134 lines):
- SM80/SM90/SM100 三代完整参数 + BI-V100 delay scaling (ns×0.5, l2w×0.6)

rle_non_trivial_runs.cuh (46→128 lines):
- SM80/SM90/SM100 三代完整参数 + key=8B(double) SM90 fallback

2026-08-03 13:14:57 +00:00

[CCCL] 瘦身 + 补全: 移除 cudax/python/libcudacxx-tests 冗余文件, 新增 c2h 测试助手 + cmake 构建系统 + 8 个 CUDA thrust examples

2026-08-03 12:39:26 +00:00

docs: CCCL → Triton methodology transfer — parameter search translation table

2026-08-03 04:37:23 +00:00

[muh] radix_sort 6%→19%, rle_encode 8%→21%, rle_non_trivial_runs 6%→18%: 完整移植 CCCL SM90/SM100 tuning tables + BI-V100 SMEM 48KB 约束

2026-08-03 13:14:57 +00:00

fix: critical config + tuning corrections from CCCL source analysis

2026-08-03 06:45:54 +00:00

qwen3_6_scripts

feat: CCCL-derived 3-tier decode dispatch + SM=16 prefill tuning + multi-step scheduling

2026-08-03 08:28:38 +00:00

feat: asymmetric BLOCK_M/BLOCK_N search + re-add BI-V100 autotune configs

2026-08-03 11:18:18 +00:00

feat: add qwen3_5.py vllm adapter for Qwen3.6-35B-A3B

2026-08-01 13:54:33 +00:00

__init__.py

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

.gitignore

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

attention.py

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

baseline.muh

[MUH] Fix three-layer disconnect — C++ headers are now the single source of truth

2026-07-30 14:12:33 +00:00

CCCL_INTEGRATION_STATUS.md

docs: CCCL integration status — 462 assets inventory, 8/8 decode hot path coverage, no-clone-more verdict

2026-08-03 03:50:24 +00:00

chat_dataset_v0.json

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

computility-run.yaml

feat: CCCL-derived 3-tier decode dispatch + SM=16 prefill tuning + multi-step scheduling

2026-08-03 08:28:38 +00:00

Dockerfile

feat: deploy CCCL-tuned prefix_prefill + muh_dispatch + fix SM=16 count

2026-08-03 08:30:16 +00:00

ENGINEX_INJECTION_MAP.md

docs: EngineX vllm injection map — Python not C++, Triton not CUDA, 32KB SMEM claim

2026-08-03 03:59:49 +00:00

enginex-vllm-bi100-qwen36-main.zip

update baseline

2026-07-30 15:19:37 +00:00

launch_service

sync: align with enginex-vllm-bi100-qwen36 baseline (1902c81f)

2026-07-31 09:43:58 +00:00

muh_dispatch.py

feat: deploy CCCL-tuned prefix_prefill + muh_dispatch + fix SM=16 count

2026-08-03 08:30:16 +00:00

muh_kernel_map.py

fix(hardware): SM count 50→16 confirmed on Phanthy Cloud BI-V100

2026-08-01 13:39:28 +00:00

MUH_PROJECT_CHECKPOINT.md

[MUH] Fix 7 structural discrepancies vs CCCL — read source, not grep

2026-07-30 14:37:38 +00:00

paged_attention_v2_pytorch.py

[FIX] V2 shape mismatch bug — v_padded used num_heads for kv_h tensor

2026-07-31 03:52:23 +00:00

paged_attention_v2_triton.py

[ARCH] CCCL-derived paged attention kernel architecture + Triton rewrite

2026-07-31 04:13:07 +00:00

paged_attn.py

sync: align with enginex-vllm-bi100-qwen36 baseline (1902c81f)

2026-07-31 09:43:58 +00:00

prefix_prefill.py

fix: revert invalid patches, add honest tuning surface assessment

2026-08-03 10:34:28 +00:00

README.md

Initial commit

2026-07-30 17:03:23 +08:00

TUNING_SURFACE_TRUTH.md

fix: revert invalid patches, add honest tuning surface assessment

2026-08-03 10:34:28 +00:00

README.md

project_6

Languages

C++ 41.8%

Cuda 31.6%

Python 22.2%

C 2.1%

CMake 1.1%

Other 1.1%