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Claude 9b0d1c283c docs: add competition server profile (4×BI-V100, Qwen3.6-35B-A3B)

Hardware: 4× Iluvatar BI-V100 32GB, Xeon Gold 6530, 503GB RAM
Software: vllm 0.6.3+corex.3.2.3, torch 2.1.0+corex.3.2.3
Model: Qwen3.6-35B-A3B at /root/public-storage/models/Qwen/
Benchmark: benchmark_server_v0.5.0.py with automated sweeps

2026-08-01 13:12:59 +00:00

cccl_upstream

[INFRA] Import NVIDIA/CCCL upstream as optimization reference library

2026-07-30 09:35:51 +00:00

docs

docs: add competition server profile (4×BI-V100, Qwen3.6-35B-A3B)

2026-08-01 13:12:59 +00:00

muh

test: add SMEM safety validator for all 26 tuning algorithms

2026-08-01 12:37:14 +08:00

optimizations

[OPT] BI-V100 Triton kernel tuning + computility-run.yaml optimization

2026-07-30 15:33:44 +00:00

qwen3_6_scripts

sync: align with enginex-vllm-bi100-qwen36 baseline (1902c81f)

2026-07-31 09:43:58 +00:00

vllm

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

__init__.py

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

.gitignore

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

attention.py

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

baseline.muh

[MUH] Fix three-layer disconnect — C++ headers are now the single source of truth

2026-07-30 14:12:33 +00:00

chat_dataset_v0.json

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

computility-run.yaml

sync: align with enginex-vllm-bi100-qwen36 baseline (1902c81f)

2026-07-31 09:43:58 +00:00

Dockerfile

[CRITICAL] Enable ixformer native V1/V2 paged attention kernels

2026-07-31 06:18:32 +00:00

enginex-vllm-bi100-qwen36-main.zip

update baseline

2026-07-30 15:19:37 +00:00

launch_service

sync: align with enginex-vllm-bi100-qwen36 baseline (1902c81f)

2026-07-31 09:43:58 +00:00

muh_dispatch.py

refactor(muh_dispatch): read-once from C++ headers, not write-twice

2026-08-01 01:30:42 +08:00

muh_kernel_map.py

[muh] fix scale_mem_bound: 3 bugs vs CCCL util_arch.cuh

2026-08-01 00:00:02 +08:00

MUH_PROJECT_CHECKPOINT.md

[MUH] Fix 7 structural discrepancies vs CCCL — read source, not grep

2026-07-30 14:37:38 +00:00

paged_attention_v2_pytorch.py

[FIX] V2 shape mismatch bug — v_padded used num_heads for kv_h tensor

2026-07-31 03:52:23 +00:00

paged_attention_v2_triton.py

[ARCH] CCCL-derived paged attention kernel architecture + Triton rewrite

2026-07-31 04:13:07 +00:00

paged_attn.py

sync: align with enginex-vllm-bi100-qwen36 baseline (1902c81f)

2026-07-31 09:43:58 +00:00

prefix_prefill.py

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

README.md

Initial commit

2026-07-30 17:03:23 +08:00

README.md

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