dylanyunlong/project_6

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dylanyunlon 84c18150e6 fix(tuning_select_if): restore 3 collapsed dispatch dimensions

Previous version collapsed 77 CCCL specializations into 4 if/else
branches by elem_size only, losing:

1. may_alias dimension: now dispatches LOAD_CA (alias-safe) vs
   LOAD_DIRECT+LOAD_LDG (no-alias, ~5-10% faster for common case).
   CCCL SM100 no-alias small-type uses BLOCK_LOAD_DIRECT.

2. has_flags dimension: flagged path now gets 2-4 fewer items_per_thread
   because flag array takes additional SMEM. SMEM check includes flag_tile.

3. delay dimension: type-size-dependent delays instead of fixed(350,450).
   Scaled from CCCL SM100 benchmarks: ns*0.5, l2w*0.6 for BI-V100 L2.

SMEM check: input_tile + output_scatter + flag_tile ≤ 48KB.

2026-08-01 02:26:48 +08:00

[INFRA] Import NVIDIA/CCCL upstream as optimization reference library

2026-07-30 09:35:51 +00:00

[muh] kernel_map: full vllm→CCCL mapping with SMEM overflow detection

2026-07-31 11:13:33 +00:00

fix(tuning_select_if): restore 3 collapsed dispatch dimensions

2026-08-01 02:26:48 +08:00

[OPT] BI-V100 Triton kernel tuning + computility-run.yaml optimization

2026-07-30 15:33:44 +00:00

qwen3_6_scripts

sync: align with enginex-vllm-bi100-qwen36 baseline (1902c81f)

2026-07-31 09:43:58 +00:00

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

__init__.py

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

.gitignore

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

attention.py

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

baseline.muh

[MUH] Fix three-layer disconnect — C++ headers are now the single source of truth

2026-07-30 14:12:33 +00:00

chat_dataset_v0.json

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

computility-run.yaml

sync: align with enginex-vllm-bi100-qwen36 baseline (1902c81f)

2026-07-31 09:43:58 +00:00

Dockerfile

[CRITICAL] Enable ixformer native V1/V2 paged attention kernels

2026-07-31 06:18:32 +00:00

enginex-vllm-bi100-qwen36-main.zip

update baseline

2026-07-30 15:19:37 +00:00

launch_service

sync: align with enginex-vllm-bi100-qwen36 baseline (1902c81f)

2026-07-31 09:43:58 +00:00

muh_dispatch.py

refactor(muh_dispatch): read-once from C++ headers, not write-twice

2026-08-01 01:30:42 +08:00

muh_kernel_map.py

[muh] fix scale_mem_bound: 3 bugs vs CCCL util_arch.cuh

2026-08-01 00:00:02 +08:00

MUH_PROJECT_CHECKPOINT.md

[MUH] Fix 7 structural discrepancies vs CCCL — read source, not grep

2026-07-30 14:37:38 +00:00

paged_attention_v2_pytorch.py

[FIX] V2 shape mismatch bug — v_padded used num_heads for kv_h tensor

2026-07-31 03:52:23 +00:00

paged_attention_v2_triton.py

[ARCH] CCCL-derived paged attention kernel architecture + Triton rewrite

2026-07-31 04:13:07 +00:00

paged_attn.py

sync: align with enginex-vllm-bi100-qwen36 baseline (1902c81f)

2026-07-31 09:43:58 +00:00

prefix_prefill.py

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

README.md

Initial commit

2026-07-30 17:03:23 +08:00

README.md

project_6

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C++ 41.8%

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Python 22.2%

C 2.1%

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