ec140f3605d2da2ed9af695c4c9f51a2e0fb7f35
cat'd every source: - CCCL c/parallel/src/reduce.cu: NVRTC JIT (cannot port directly) - CCCL c/parallel.v2/src/reduce.cu: hostjit/libnvcc (cannot port directly) - CUB block/warp headers: pure header-only (CAN compile with corex) - CUTLASS SM70 SIMT GEMM: CAN port (example 24 grouped_gemm) - FlashAttention: SM80 Tensor Core (cannot port), but layer_norm is SIMT - FLA: pure Triton (needs corex Triton verification) - xllm ILU: all already ported Key finding: CCCL c/parallel depends on nvrtc JIT — must bypass with AOT compilation using CUB header-only API + corex clang --cuda-gpu-arch=ivcore10
project_6
Description
Languages
C++
41.8%
Cuda
31.6%
Python
22.2%
C
2.1%
CMake
1.1%
Other
1.1%