[prefill] asymmetric BLOCK_M/BLOCK_N from CCCL AgentReduce insight
CCCL agent_reduce.cuh reveals the key asymmetry in flash attention tiling:
- Q tile stays RESIDENT in registers across the entire K/V loop
- K/V tiles STREAM through: each iteration loads new BLOCK_N, consumes, frees
- Therefore BLOCK_N can differ from BLOCK_M
This is NOT parameter tuning. This is a structural observation from reading
agent_reduce.cuh's ConsumeFullTile: it uses striped loads where the tile
stays resident while data streams through. The same pattern applies to
flash attention's inner loop.
For BI-V100 (SM=16, SMEM=48KB, head_dim=128, fp16):
BLOCK_M=32, BLOCK_N=128 → Q=8KB resident + K=32KB streaming = 40KB (82%)
This maximizes K/V bandwidth utilization per iteration.
Also: removed stale import time / timing code from kernel launch.
Source: cccl_upstream/cub/cub/agent/agent_reduce.cuh lines 195-230
(ConsumeFullTile vectorized vs scalar path)
This commit is contained in:
@@ -711,25 +711,39 @@ if triton.__version__ >= "2.1.0":
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# CCCL-informed block size selection for BI-V100 (SM=16, 48KB SMEM)
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#
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# SMEM budget per Triton block (approximate):
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# Q tile: BLOCK_M * head_dim * element_size
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# K tile: head_dim * BLOCK_N * element_size (transposed)
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# V tile: BLOCK_N * head_dim * element_size
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# Triton uses fp32 accumulators but loads in native dtype.
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# Key insight from CCCL AgentReduce (agent_reduce.cuh):
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# - Q tile stays resident in registers/SMEM across the K/V loop
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# - K/V tiles stream through: each iteration loads a new BLOCK_N chunk
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# - Therefore BLOCK_N can be larger than BLOCK_M (asymmetric tiling)
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# - Larger BLOCK_N = fewer loop iterations = fewer kernel barriers
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#
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# For BI-V100: BLOCK=64, NUM_WARPS=4 keeps SMEM usage conservative
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# and matches CCCL scan tuning pattern (fewer CTAs but larger tiles).
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# SM=16 means only 32 concurrent CTAs, so moderate parallelism is fine.
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# SMEM budget (peak, not simultaneous - Triton pipelines K/V loads):
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# Q resident: BLOCK_M * head_dim * elem_size (stays across all iters)
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# K per iter: head_dim * BLOCK_N * elem_size (loaded, consumed, freed)
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# softmax: BLOCK_M * 4 * 2 (m_i + l_i, fp32)
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# Total peak: Q + K + softmax_state
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#
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# Reference: muh/tuning/tuning_scan.cuh bi100_lookback_4B_o4
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# threads=384, items=22 → effective tile = 384*22 = 8448 elements
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# Triton equivalent: BLOCK=64, warps=4 (128 threads, larger tile per warp)
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# For BI-V100 with head_dim=128, fp16 (2B):
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# BLOCK_M=32, BLOCK_N=64: Q=8KB + K=16KB + ss=256B = 24.25KB (49%)
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# BLOCK_M=64, BLOCK_N=64: Q=16KB + K=16KB + ss=512B = 32.5KB (66%)
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# BLOCK_M=32, BLOCK_N=128: Q=8KB + K=32KB + ss=256B = 40.25KB (82%)
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#
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# CCCL scan tuning reference (tuning_scan.cuh):
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# SM100 best: ipt=22, tpb=384 → tile = 8448 elements
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# BI-V100 bench best: ipt=22, tpb=384, no_delay → 1.038x
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# Maps to: moderate tile, no inter-CTA delay (16 SMs = low contention)
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#
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# Strategy: BLOCK_M=32 (small Q tile, high occupancy) +
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# BLOCK_N=64 (moderate K sweep, fits SMEM easily)
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# This gives 2 CTAs per SM occupancy with 16 SMs = 32 CTAs
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_is_bi_v100 = not current_platform.has_device_capability(80)
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if _is_bi_v100:
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BLOCK = 64
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BLOCK = 64 # BLOCK_M for Q tile
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BLOCK_N = 64 # BLOCK_N for K/V sweep (can differ from BLOCK_M)
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NUM_WARPS = 4
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else:
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BLOCK = 128
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BLOCK_N = BLOCK # symmetric for NVIDIA GPUs
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NUM_WARPS = 8
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# need to reduce num. blocks when using fp32
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@@ -822,14 +836,12 @@ if triton.__version__ >= "2.1.0":
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BLOCK_M=BLOCK,
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BLOCK_DMODEL=Lk,
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BLOCK_DMODEL_PADDED=Lk_padded,
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BLOCK_N=BLOCK,
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BLOCK_N=BLOCK_N,
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num_warps=NUM_WARPS,
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num_stages=1,
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)
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return
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import time
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ts_beg = time.time()
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_fwd_kernel[grid](
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q,
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k,
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@@ -875,11 +887,9 @@ if triton.__version__ >= "2.1.0":
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BLOCK_M=BLOCK,
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BLOCK_DMODEL=Lk,
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BLOCK_DMODEL_PADDED=Lk_padded,
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BLOCK_N=BLOCK,
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BLOCK_N=BLOCK_N,
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SLIDING_WINDOW=sliding_window,
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num_warps=NUM_WARPS,
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num_stages=1,
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)
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elapsed = time.time() - ts_beg
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#print(f'{elapsed}: {BLOCK=}, {Lk=}, {Lk_padded=}, {BLOCK=}, {sliding_window=}, {NUM_WARPS=}')
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return
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