dylanyunlong/project_6

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project6-dev 905bf4db2c feat(moe): wire silu_and_mul through C++ bridge in corex_moe.py

Now MoE activation uses:
  Tier 0: ix_bridge.silu_and_mul (C++ ixformer_torch_ext, verified on BI-V100)
  Tier 1: ixformer.functions.silu_and_mul (Python)
  Tier 2: F.silu(gate) * up (pure PyTorch)

Verified 7/8 on single BI-V100:
  ✓ compile, silu_and_mul, rms_norm, fused_add_rms_norm, linear, paged_attn, corex_moe
  ✗ flash_attn import path (not needed, vllm xformers backend handles it)

2026-08-10 06:36:40 +00:00

feat(cccl): integrate missing CCCL directories — python/, ci/, .agent/, docs/, test/

2026-08-07 02:34:33 +00:00

[docs] CCCL ↔ EngineX architecture alignment — from reading 3792 CCCL source files

2026-08-06 06:02:40 +00:00

feat(moe): wire silu_and_mul through C++ bridge in corex_moe.py

2026-08-10 06:36:40 +00:00

test: add scan tuning verification — union SMEM model from agent_scan.cuh

2026-08-07 03:16:44 +00:00

fix: critical config + tuning corrections from CCCL source analysis

2026-08-03 06:45:54 +00:00

qwen3_6_scripts

fix: add error logging to all corex module imports + dtype guard

2026-08-10 04:51:16 +00:00

ref(upstream): FULL TREE — Deep-Spark xllm (1470) + ds_vllm csrc/models (703)

2026-08-10 02:54:03 +00:00

fix(d05): CCCL graceful degradation — strip image_url for non-multimodal models

2026-08-07 09:01:48 +00:00

feat: add qwen3_5.py vllm adapter for Qwen3.6-35B-A3B

2026-08-01 13:54:33 +00:00

__init__.py

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

.dockerignore

fix(build): add .dockerignore + safe probe — fix docker build failure

2026-08-08 11:21:43 +00:00

.gitignore

[muh] gen_patch: expand VLLM_INJECTION_POINTS to full real injection surface

2026-08-06 04:01:40 +00:00

attention.py

[ENGINE] attention.py: CCCL dispatch_reduce.cuh single-tile decision for V1/V2

2026-08-07 01:54:40 +00:00

baseline.muh

fix(critical): disable thinking for tool_call requests — fixes d03_tool_call FAIL

2026-08-07 07:45:28 +00:00

BI_V100_BENCHMARK_RUNBOOK.md

[docs] BI-V100 benchmark runbook: Phase 0 硬件探测 + Phase 1 quick sweep + Phase 3 端到端验证

2026-08-04 01:14:30 +00:00

CCCL_ASSET_MAP.md

[CCCL] Add missing CCCL components: c2h, nvbench_helper, cmake, cudax, AGENTS.md

2026-08-06 02:14:18 +00:00

CCCL_INTEGRATION_STATUS.md

docs: CCCL integration status — 462 assets inventory, 8/8 decode hot path coverage, no-clone-more verdict

2026-08-03 03:50:24 +00:00

CCCL_MUH_GAP_ANALYSIS.md

analysis: 26-algorithm CCCL↔muh full gap scan — 19.7% coverage, 299 benchmark points needed, 3/26 READY

2026-08-07 02:43:04 +00:00

CCCL_MUH_PARITY_AUDIT.md

audit: CCCL vs muh parity check — scale_mem_bound 11/11 PASS, SM100 benchmark values extracted

2026-08-07 07:19:00 +00:00

CCCL_PATTERN_MAP.md

docs: CCCL → vllm kernel pattern mapping for competition

2026-08-07 03:19:39 +00:00

cccl_sm100_benchmark_values.json

audit: CCCL vs muh parity check — scale_mem_bound 11/11 PASS, SM100 benchmark values extracted

2026-08-07 07:19:00 +00:00

CCCL_TUNING_GAP_REPORT.md

[analysis] CCCL↔muh 26-algorithm tuning gap report — 294 bench pts needed, 19% line coverage, reduce/scan/topk P0

2026-08-07 01:45:37 +00:00

chat_dataset_v0.json

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

CODEPATH_MAP.md

doc: add functional test FAIL root cause analysis to CODEPATH_MAP

2026-08-09 00:03:45 +00:00

COMPETITIVE_ANALYSIS_AND_FIX_PLAN.md

fix(critical): disable thinking for tool_call requests — fixes d03_tool_call + d05/t5 FAIL

2026-08-07 08:45:22 +00:00

computility-run.yaml

fix(CRITICAL): CCCL overflow guard — clamp before cumsum + max-num-seqs=2

2026-08-08 21:49:39 +00:00

deltanet_chunk_optimize.py

[CCCL-PORT] Two architecture-level optimizations from CCCL system design

2026-08-05 08:20:01 +00:00

DLOPEN_DISPATCH_CHAIN.md

feat(EX): corex_gdn + corex_moe — dlopen dispatch chain from comp 168 log analysis

2026-08-10 03:37:15 +00:00

Dockerfile

fix(EX): corex ivcore10 build flags + deploy pipeline + topk kernel cleanup

2026-08-10 02:31:55 +00:00

dockerrizhi.txt

comp 168 docker

2026-08-07 08:43:51 +00:00

engine_cccl_patterns.py

[ENGINE] Pattern 7: CCCL C API JIT → Triton autotune mapping

2026-08-06 02:32:34 +00:00

ENGINE_CODEPATH_TIMELINE.md

arch(CoreX): CCCL env_dispatch — try native fused kernels, fallback PyTorch

2026-08-08 11:15:04 +00:00

ENGINEX_INJECTION_MAP.md

docs: EngineX vllm injection map — Python not C++, Triton not CUDA, 32KB SMEM claim

2026-08-03 03:59:49 +00:00

enginex-vllm-bi100-qwen36-main.zip

update baseline

2026-07-30 15:19:37 +00:00

GROUND_TRUTH_STATUS_v2.md

[DOC] GROUND_TRUTH_STATUS v2 — based on complete code reading

2026-08-06 02:21:03 +00:00

GROUND_TRUTH_STATUS.md

[STATUS] Ground truth: gen_patch C++ injection dead, real path is Triton+Python tuning

2026-08-05 07:57:53 +00:00

HARDWARE_PROBE_20260808.md

doc: BI-V100 hardware probe raw data (SSH Aug 8 2026)

2026-08-08 18:18:48 +00:00

launch_service

sync: align with enginex-vllm-bi100-qwen36 baseline (1902c81f)

2026-07-31 09:43:58 +00:00

muh_cc_dispatch.py

[ENGINE] muh_cc_dispatch + analysis: max_num_seqs=1 from computility-run.yaml

2026-08-06 01:02:21 +00:00

muh_dispatch.py

[muh_dispatch] 修正 head_dim=128→256 + 删除死代码 + 强制 V1

2026-08-05 07:12:26 +00:00

muh_kernel_map.py

[docs+code] lookback delay is a no-op on BI-V100 + V2 compound reduce pattern

2026-08-05 03:35:07 +00:00

MUH_PROJECT_CHECKPOINT.md

[MUH] Fix 7 structural discrepancies vs CCCL — read source, not grep

2026-07-30 14:37:38 +00:00

MUH_TUNING_GAP_ANALYSIS.md

docs: comprehensive CCCL vs muh gap analysis with competition priority

2026-08-07 03:18:25 +00:00

paged_attention_v2_pytorch.py

[ENGINE] paged_attention_v2: CCCL single-tile fast path + GridEvenShare constants

2026-08-06 02:21:29 +00:00

paged_attention_v2_triton.py

[ARCH] CCCL-derived paged attention kernel architecture + Triton rewrite

2026-07-31 04:13:07 +00:00

paged_attn.py

fix(critical): raise decode threshold to prevent service crash

2026-08-07 04:39:19 +00:00

PIPELINE_GROUND_TRUTH.md

docs: pipeline ground truth — CCCL parity audit, SM100 benchmark data, injection status

2026-08-07 07:20:34 +00:00

PIPELINE_REALITY_CHECK.md

feat: add gen_config.py (Python-layer config generator) + pipeline reality check

2026-08-07 03:11:56 +00:00

PIPELINE_STATUS.md

docs: add PIPELINE_STATUS.md — ground truth for muh injection mapping and toolchain status

2026-08-07 01:45:46 +00:00

PRD.md

doc(prd): complete base engine migration checklist

2026-08-08 10:48:43 +00:00

prefix_prefill.py

[prefill] asymmetric BLOCK_M/BLOCK_N from CCCL AgentReduce insight

2026-08-05 03:07:20 +00:00

probe_all_symbols.sh

debug: probe all ixformer symbol locations

2026-08-10 06:33:14 +00:00

probe_ixformer_symbols.py

fix: fail-fast on ix_bridge failure + probe script for real machine

2026-08-10 03:04:50 +00:00

probe_symbol.sh

debug: probe script to find silu_and_mul symbol location

2026-08-10 06:32:04 +00:00

PROJECT_SUMMARY.md

docs: update PROJECT_SUMMARY.md — corex rewrite + dispatch chain analysis

2026-08-10 06:17:38 +00:00

README.md

Initial commit

2026-07-30 17:03:23 +08:00

SUB509_DEEP_DIAGNOSIS.md

fix(deltanet): systematic NaN elimination via CCCL overflow_cast pattern

2026-08-07 09:26:11 +00:00

SUB509_DIAGNOSIS.md

docs: complete sub508 diagnosis — 19 cascade failures from n=2, full test matrix

2026-08-07 07:54:09 +00:00

subrizhi.txt

comp 168 submit

2026-08-07 07:47:01 +00:00

SYSTEM_DESIGN.md

doc: system design — architecture, file map, data flow, build pipeline

2026-08-10 02:07:43 +00:00

TUNING_SURFACE_TRUTH.md

fix: revert invalid patches, add honest tuning surface assessment

2026-08-03 10:34:28 +00:00

verify_on_device.py

test: verify_on_device.py — 真机逐函数验证, 不允许fallback

2026-08-10 04:06:21 +00:00

verify_single_gpu.py

refactor(bridge): rewrite ix_full_bridge.cpp for actual base image symbols

2026-08-10 06:34:54 +00:00

README.md

project_6

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C++ 41.8%

Cuda 31.6%

Python 22.2%

C 2.1%

CMake 1.1%

Other 1.1%