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对齐xllm系统设计 (qwen3_gated_delta_net_base.cpp): 1. Gate计算前置clamp（xllm fused_gdn_gating threshold=20.0f）: - prefill: g = (-A_log.exp() * softplus(a + dt_bias)).clamp(-20, 20) - decode: 同上 不再需要后置clamp——源头控制数值范围 2. Prefill走flash_qla_sm70 CUDA kernel（xllm chunk_gated_delta_rule等价）: - flash_qla_sm70_gdn_strided.so (10MB, Step 7已编译) - chunk_gated_delta_rule_fwd_sm70(q, k, v, g, beta, initial_state) - Python _torch_chunk_gated_delta_rule仅在kernel不可用时使用 3. Decode继续走5个corex .so: corex_gdn_causal_conv, corex_gdn_packed_decode, corex_gdn_beta_decay, corex_gdn_qk_map, corex_gdn_gated_norm