4d9165fa30
tuning_transform_tile.cuh entire design (90 lines):
pick_tile_size() computes optimal tile dimensions from:
- Hardware: threads_per_block=128, vector_bytes=16 (LDG.E.128),
max_occupancy=16, cc_to_min_bytes_in_flight(cc)
- Data types: min(sizeof(Out), sizeof(Ins)...) → items_for_vec
- Latency: target / (occupancy × threads × bytes) → items_for_latency
- Result: max(vec, latency) rounded to power_of_2, capped at 32
- Special: MUFU-heavy ops with small types → reduce items/thread
Key insight: tile size is DERIVED, not hardcoded.
Translation to _HardwarePolicy.detect():
Previous: deltanet_chunk_size = 64 (hardcoded), prefill_chunk = 4096
Now: chunk_size derived from solve_triangular availability:
- solve_tri available → 64 (amortize launch, like CCCL max_items)
- solve_tri unavailable → 32 (fewer Python iterations, like CCCL
MUFU-heavy reduction for sub-4B ops)
prefill_chunk stays 4096 but with documented derivation from
BI-V100 memory budget (matching CCCL's bytes_in_flight target).
CCCL source: cub/cub/device/dispatch/tuning/tuning_transform_tile.cuh
Maps to: qwen3_6_scripts/qwen3_5.py (_HardwarePolicy)