muh-engine 8c969ce7dc [ENGINE] paged_attn.py: CCCL dispatch_reduce architecture port
Three changes from reading CCCL dispatch_reduce.cuh + kernel_reduce.cuh +
agent_reduce.cuh + grid_even_share.cuh + summary_statistics.cu:

1. V2 dispatch restored (was hardcoded use_v1=True)
   CCCL two-path: single-tile vs multi-tile (GridEvenShare).
   Threshold now uses BI-V100 SM count (16) for saturation calc.

2. _forward_decode_pytorch rewritten with CCCL patterns:
   agent_reduce ConsumeFullTile: reduced .contiguous() from 4 to 2.
   GridEvenShare RAKE tiling: adaptive _MAX_TILE_BLOCKS=1024.
   summary_statistics.cu compound reduce: online softmax {m,l,o}.

3. KV gather: permute(1,2,4,0,3) for K avoids intermediate alloc.

CCCL files read: dispatch_reduce.cuh, kernel_reduce.cuh,
agent_reduce.cuh, grid_even_share.cuh, summary_statistics.cu,
kernel_scan.cuh
2026-08-05 09:22:46 +00:00
2026-07-30 17:03:23 +08:00

project_6

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