dylanyunlong/project_6

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muh-pipeline 8056641f08 [BASE] qwen3_6_scripts/xformers.py: CCCL block_load_to_shared pre-alloc pattern

Random CCCL pick: cub/cub/block/block_load_to_shared.cuh (340 lines, full read)

CCCL's BlockLoadToShared reveals three-tier hardware dispatch:
  SM90+: cp.async.bulk (TMA) — one instruction copies entire tile
  SM80+: cp.async.cg — 16B aligned async copy, bypasses L1
  SM70-: manual gmem→reg→smem fallback (vec_load_t 16B chunks)

BI-V100 (non-NVIDIA) takes the fallback path. This explains why all
competitors are stuck at 1560 max (vs 8000 target) — no async copy
hardware acceleration.

Applied CCCL pre-allocation pattern to _run_sdpa_fallback:
  - k_pos = torch.arange(q_len) computed once per sequence (was correct
    already but now documented why via CCCL mbarrier_init-before-loop)
  - Added note about CommitToken pattern for mask caching

Also confirmed: _Q_CHUNK=256 is reasonable for BI-V100 given
  256 × 256 × 4B = 256KB attention matrix fits in available memory.

Base file modified: qwen3_6_scripts/xformers.py (deployed via patch_ops.sh)

2026-08-06 02:51:48 +00:00

[CCCL] Add missing CCCL components: c2h, nvbench_helper, cmake, cudax, AGENTS.md

2026-08-06 02:14:18 +00:00

[DOCS] CCCL benchmark reference: 199 annotations from 27 tuning files extracted

2026-08-06 02:16:42 +00:00

[ENGINE] scan tuning: document GridThreshold=500 gate from CCCL source

2026-08-06 02:22:13 +00:00

fix: critical config + tuning corrections from CCCL source analysis

2026-08-03 06:45:54 +00:00

qwen3_6_scripts

[BASE] qwen3_6_scripts/xformers.py: CCCL block_load_to_shared pre-alloc pattern

2026-08-06 02:51:48 +00:00

[BASE] vllm/core/evictor_v2.py: CCCL bucket_sort2d design pattern annotation

2026-08-06 02:29:19 +00:00

feat: add qwen3_5.py vllm adapter for Qwen3.6-35B-A3B

2026-08-01 13:54:33 +00:00

__init__.py

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

.gitignore

[housekeeping] add enginex_base/ to gitignore — 解压后的基础引擎仅供本地分析

2026-08-05 07:17:37 +00:00

attention.py

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

baseline.muh

[MUH] Fix three-layer disconnect — C++ headers are now the single source of truth

2026-07-30 14:12:33 +00:00

BI_V100_BENCHMARK_RUNBOOK.md

[docs] BI-V100 benchmark runbook: Phase 0 硬件探测 + Phase 1 quick sweep + Phase 3 端到端验证

2026-08-04 01:14:30 +00:00

CCCL_ASSET_MAP.md

[CCCL] Add missing CCCL components: c2h, nvbench_helper, cmake, cudax, AGENTS.md

2026-08-06 02:14:18 +00:00

CCCL_INTEGRATION_STATUS.md

docs: CCCL integration status — 462 assets inventory, 8/8 decode hot path coverage, no-clone-more verdict

2026-08-03 03:50:24 +00:00

chat_dataset_v0.json

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

computility-run.yaml

[CRITICAL] yaml 恢复到基础引擎原版——先通过功能测试再优化性能

2026-08-05 07:47:07 +00:00

deltanet_chunk_optimize.py

[CCCL-PORT] Two architecture-level optimizations from CCCL system design

2026-08-05 08:20:01 +00:00

Dockerfile

[SIMPLIFY] Dockerfile 恢复到基础引擎原版 4 行——所有适配通过 patch_ops.sh

2026-08-05 07:14:23 +00:00

engine_cccl_patterns.py

[ENGINE] Pattern 7: CCCL C API JIT → Triton autotune mapping

2026-08-06 02:32:34 +00:00

ENGINEX_INJECTION_MAP.md

docs: EngineX vllm injection map — Python not C++, Triton not CUDA, 32KB SMEM claim

2026-08-03 03:59:49 +00:00

enginex-vllm-bi100-qwen36-main.zip

update baseline

2026-07-30 15:19:37 +00:00

GROUND_TRUTH_STATUS_v2.md

[DOC] GROUND_TRUTH_STATUS v2 — based on complete code reading

2026-08-06 02:21:03 +00:00

GROUND_TRUTH_STATUS.md

[STATUS] Ground truth: gen_patch C++ injection dead, real path is Triton+Python tuning

2026-08-05 07:57:53 +00:00

launch_service

sync: align with enginex-vllm-bi100-qwen36 baseline (1902c81f)

2026-07-31 09:43:58 +00:00

muh_cc_dispatch.py

[ENGINE] muh_cc_dispatch + analysis: max_num_seqs=1 from computility-run.yaml

2026-08-06 01:02:21 +00:00

muh_dispatch.py

[muh_dispatch] 修正 head_dim=128→256 + 删除死代码 + 强制 V1

2026-08-05 07:12:26 +00:00

muh_kernel_map.py

[docs+code] lookback delay is a no-op on BI-V100 + V2 compound reduce pattern

2026-08-05 03:35:07 +00:00

MUH_PROJECT_CHECKPOINT.md

[MUH] Fix 7 structural discrepancies vs CCCL — read source, not grep

2026-07-30 14:37:38 +00:00

paged_attention_v2_pytorch.py

[ENGINE] paged_attention_v2: CCCL single-tile fast path + GridEvenShare constants

2026-08-06 02:21:29 +00:00

paged_attention_v2_triton.py

[ARCH] CCCL-derived paged attention kernel architecture + Triton rewrite

2026-07-31 04:13:07 +00:00

paged_attn.py

[ENGINE] paged_attn V2: CCCL agent_merge_sort union TempStorage cache

2026-08-06 01:04:01 +00:00

prefix_prefill.py

[prefill] asymmetric BLOCK_M/BLOCK_N from CCCL AgentReduce insight

2026-08-05 03:07:20 +00:00

README.md

Initial commit

2026-07-30 17:03:23 +08:00

TUNING_SURFACE_TRUTH.md

fix: revert invalid patches, add honest tuning surface assessment

2026-08-03 10:34:28 +00:00

README.md

project_6

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C++ 41.8%

Cuda 31.6%

Python 22.2%

C 2.1%

CMake 1.1%

Other 1.1%