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project_6 5ca49d0e7c [docs] GridEvenShare work distribution — BI-V100 attention reduce needs only 9 CTAs

From reading cccl_upstream/cub/cub/grid/grid_even_share.cuh:

Key finding: For Qwen3.6 attention score reduction (100K seq_len),
with tile_items=12288 (512 threads × 24 items), only 9 CTAs are
needed. All fit in one wave on 16 SMs.

This means reduce tuning (items/threads) matters less than the V1/V2
dispatch choice in paged_attn.py. V1 uses a single CTA iterating
sequentially over all KV blocks, completely bypassing GridEvenShare's
parallel distribution. V2 would enable partition-based parallelism.

Also documents: RAKE (scan) vs STRIP_MINE (reduce) strategies,
'big shares' load balancing, and the SingleTile fast path for
short sequences.

2026-08-05 03:36:45 +00:00

[CCCL] 瘦身 + 补全: 移除 cudax/python/libcudacxx-tests 冗余文件, 新增 c2h 测试助手 + cmake 构建系统 + 8 个 CUDA thrust examples

2026-08-03 12:39:26 +00:00

[docs] GridEvenShare work distribution — BI-V100 attention reduce needs only 9 CTAs

2026-08-05 03:36:45 +00:00

[gen_patch] Replace dead .cu injection points with real Triton/config targets

2026-08-05 03:36:37 +00:00

fix: critical config + tuning corrections from CCCL source analysis

2026-08-03 06:45:54 +00:00

qwen3_6_scripts

feat: CCCL-derived 3-tier decode dispatch + SM=16 prefill tuning + multi-step scheduling

2026-08-03 08:28:38 +00:00

[v2] PARTITION_SIZE 512→1024 + fix import path

2026-08-05 03:32:23 +00:00

feat: add qwen3_5.py vllm adapter for Qwen3.6-35B-A3B

2026-08-01 13:54:33 +00:00

__init__.py

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

.gitignore

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

attention.py

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

baseline.muh

[MUH] Fix three-layer disconnect — C++ headers are now the single source of truth

2026-07-30 14:12:33 +00:00

BI_V100_BENCHMARK_RUNBOOK.md

[docs] BI-V100 benchmark runbook: Phase 0 硬件探测 + Phase 1 quick sweep + Phase 3 端到端验证

2026-08-04 01:14:30 +00:00

CCCL_INTEGRATION_STATUS.md

docs: CCCL integration status — 462 assets inventory, 8/8 decode hot path coverage, no-clone-more verdict

2026-08-03 03:50:24 +00:00

chat_dataset_v0.json

[DEPLOY] Complete submission: baseline + all optimizations

2026-07-30 16:06:20 +00:00

computility-run.yaml

[yaml+prefill] num-scheduler-steps 8→16 from CCCL delay analysis

2026-08-05 03:16:06 +00:00

Dockerfile

feat: deploy CCCL-tuned prefix_prefill + muh_dispatch + fix SM=16 count

2026-08-03 08:30:16 +00:00

ENGINEX_INJECTION_MAP.md

docs: EngineX vllm injection map — Python not C++, Triton not CUDA, 32KB SMEM claim

2026-08-03 03:59:49 +00:00

enginex-vllm-bi100-qwen36-main.zip

update baseline

2026-07-30 15:19:37 +00:00

launch_service

sync: align with enginex-vllm-bi100-qwen36 baseline (1902c81f)

2026-07-31 09:43:58 +00:00

muh_dispatch.py

feat: deploy CCCL-tuned prefix_prefill + muh_dispatch + fix SM=16 count

2026-08-03 08:30:16 +00:00

muh_kernel_map.py

[docs+code] lookback delay is a no-op on BI-V100 + V2 compound reduce pattern

2026-08-05 03:35:07 +00:00

MUH_PROJECT_CHECKPOINT.md

[MUH] Fix 7 structural discrepancies vs CCCL — read source, not grep

2026-07-30 14:37:38 +00:00

paged_attention_v2_pytorch.py

[v2] Phase 2 kernel fusion: save 1 division launch + CCCL sources read

2026-08-05 03:35:14 +00:00

paged_attention_v2_triton.py

[ARCH] CCCL-derived paged attention kernel architecture + Triton rewrite

2026-07-31 04:13:07 +00:00

paged_attn.py

[v2] Wire paged_attention_v2_pytorch into vllm — enable V2 for long sequences

2026-08-05 03:26:18 +00:00

prefix_prefill.py

[prefill] asymmetric BLOCK_M/BLOCK_N from CCCL AgentReduce insight

2026-08-05 03:07:20 +00:00

README.md

Initial commit

2026-07-30 17:03:23 +08:00

TUNING_SURFACE_TRUTH.md

fix: revert invalid patches, add honest tuning surface assessment

2026-08-03 10:34:28 +00:00

README.md

project_6

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C++ 41.8%

Cuda 31.6%

Python 22.2%

C 2.1%

CMake 1.1%

Other 1.1%