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Documents the three-layer mapping between CCCL's device-level API (dispatch/kernel/agent) and EngineX's actual execution surface (precompiled .so + Triton JIT + Python runtime). Key finding: EngineX has ZERO .cu source files. All CUDA kernels are precompiled in 3 .so files. Our optimization surface is: 1. Python runtime params (paged_attn.py, _custom_ops.py) 2. Triton JIT kernels (flash_attention, rmsnorm, rope, splitk) 3. Server config (computility-run.yaml) CCCL patterns applied: - GridEvenShare (grid_even_share.cuh) → V1/V2 dispatch + tile sizing - Compound reduce (summary_statistics.cu) → online softmax accumulator - Two-phase reduce (kernel_reduce.cuh) → paged_attention_v2 partition/merge - spread_out_items_per_thread (dispatch_transform.cuh) → Triton BLOCK_SIZE - Lookback delay (tuning_scan.cuh) → no_delay optimal for 16 SMs Source: read agent_reduce.cuh (425 lines), kernel_reduce.cuh (290 lines), dispatch_reduce.cuh (530 lines), grid_even_share.cuh (180 lines), dispatch_transform.cuh (250 lines), kernel_scan.cuh (175 lines), tuning_reduce.cuh (478 lines), common.cuh (330 lines), flash_attention.py (230 lines), rmsnorm_kernels.py (140 lines), triton_splitk.py (739 lines), prefix_prefill.py (866 lines)