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Author SHA1 Message Date
root
fedb48f21e [feat] baseline5 fused linear+allreduce bridge 2026-08-20 08:48:21 +00:00
root
ab078989da [fix] reshape_paged_cache slot_mapping int64→int32 (C++ data_ptr<int>要求) 2026-08-18 07:41:38 +00:00
root
9e1df1482e [fix] xllm_ops 5处C++参数签名 2026-08-18 07:10:18 +00:00
root
c92135111e [fix] reshape_paged_cache参数顺序 2026-08-18 06:44:01 +00:00
root
b89bd3d72f [fix] ix_moe_bridge pybind名无ix_前缀: ix_paged_attention→paged_attention, ix_linear→linear 2026-08-18 06:14:15 +00:00
root
54a9b572af [fix] xllm_ops 7处函数名匹配.so真实导出符号 
- reshape_and_cache → reshape_paged_cache (xllm_cache.so)
- residual_rms_norm → fused_add_rms_norm (xllm_norm.so)
- topk_softmax → moe_fused_topk (xllm_moe.so)
- moe_compute_token_index → moe_compute_index (xllm_moe.so)
- ix_full_bridge → ix_moe_bridge (paged_attention, ix_linear)
- ix_linear 5参数 → 3参数 (input, weight, bias)
- check_all: ix_moe_bridge改为required, ix_full_bridge改为optional
 2026-08-18 06:11:03 +00:00
root
fccb78df09 Merge branch 'main' of https://dev.modelhub.org.cn/dylanyunlong/project_6 into main 2026-08-18 04:17:58 +00:00
root
8cc6a91b8a [fix] baseline4 use ix_moe_bridge.so instead of broken ix_full_bridge.so 2026-08-18 04:17:37 +00:00
root
13b12aac4c [fix] baseline4 rms_norm crash 2026-08-18 03:35:26 +00:00
Claude
b77743451c debug: rms_norm weight.dim()!=1 — 打印前20次调用的w.shape, x.shape, class 2026-08-18 02:08:37 +00:00
root
c655c1d29e fix: replace symlinks with real files for Docker build 2026-08-17 10:52:34 +00:00
root
f10cccf9df [fix] baseline4 :ix_moe_bridge.so 。 v2 bridge 真机编译通过，13函数全导出 2026-08-17 09:18:32 +00:00
Claude
7d6884d15a tool: verify_bridge.sh — 验证prebuilt .so是v1还是v2，缺MoE则自动重编 
5步验证流程:
  Step 1: 定位 prebuilt ix_full_bridge.so
  Step 2: nm -D 检查导出符号 (v1=5函数 vs v2=13函数)
  Step 3: 检查编译源文件+工具链+依赖库
  Step 4: 缺MoE函数则调用 build_moe_bridge.sh 重编
  Step 5: Python import 验证最终 .so 的函数列表
 2026-08-17 08:49:14 +00:00
root
b342eb6b98 [fix] baseline4 fix prebuilt ix_full_bridge.so 大概率是从 v2 编译的 2026-08-17 08:26:54 +00:00
root
ba127fe66b delay baseline4 docker build 2026-08-17 07:39:52 +00:00
root
512f384a49 Merge branch 'main' of https://dev.modelhub.org.cn/dylanyunlong/project_6 into main 2026-08-17 04:19:31 +00:00
root
cdcf115037 feat: CUTLASS Cu10 grouped GEMM — real device verified 
BI-V100 real device results:
  moe_group_gemm: err=0.000015 PASS
  moe_decode_cutlass: NaN=False PASS
  cutlass grouped: 4.77ms vs torch.mm loop: 9.38ms → 1.97x speedup

Fix: gemm_grouped.cu ldb=K (not N) for ColumnMajor B view
Link: -lcuinfer from /usr/local/corex-3.2.3/lib64/libcuinfer.so.7
 2026-08-17 04:18:29 +00:00
root
beaa8dbb65 Merge branch 'main' of https://dev.modelhub.org.cn/dylanyunlong/project_6 2026-08-17 02:18:46 +00:00
root
03be5f2b15 [feat] group gemm 2026-08-17 02:16:58 +00:00
project_6
415ca12afc fix: group_gemm format "TN" + Layer 3 ops_api dispatch from xllm upstream 
AST chain alignment with upstream_ref/xllm/xllm/core/kernels/ilu/:

Layer 5: ixformer::infer (binary .so on device)
Layer 4: xllm_kernels/ilu/*.cpp -> calls ixformer::infer (0-diff with upstream)
Layer 3: xllm_kernels/ops_api.h+cpp + param.h (NEW from upstream 2719 lines)
         kernels/kernels.h aggregation header (NEW)
Layer 2: xllm_layers/ilu/*.cpp (0-diff with upstream)
Layer 1: ix_full_bridge_v2.cpp pybind11 bridge (FIXED)

Critical fixes in ix_full_bridge_v2.cpp:
- group_gemm format "default" -> "TN" (match upstream ilu/group_gemm.cpp)
- fused_moe_forward: pass 3D weights directly instead of .view({-1,...})
- group_gemm output_n: use tokens_per_experts.sum() per upstream convention
 2026-08-16 16:09:15 +00:00
Claude
6415249693 data: port complete MoE + xllm layer call chains from upstream repos 
MoE call chain from ds_vllm (vllm-project/vllm latest):
  ex_engine/moe/ — 20 files, 8736 lines
  - modular_kernel.py (1630 lines) — base classes for modular MoE
  - experts/fused_batched_moe.py (972 lines) — NaiveBatchedExperts
  - prepare_finalize/batched.py (171 lines) — token grouping by expert
  - topk_weight_and_reduce.py (176 lines) — scatter-add finalize
  - fused_moe.py (1740 lines) — main fused_moe dispatch
  - config.py (1407 lines) — FusedMoEQuantConfig
  - activation.py, utils.py, layer.py, etc.

xllm layer code (jd-opensource/xllm):
  ex_engine/xllm_layers/ — 39 files, 5859 lines
  - ilu/fused_moe.cpp (797 lines) — production ixformer 7-step MoE pipeline
  - ilu/attention.cpp (189 lines) — paged_attention + flash_attn bridge
  - npu_torch/qwen3_gated_delta_net_base.cpp (576 lines) — GDN reference
  - common/rms_norm.cpp, rotary_embedding.cpp, activation.cpp, dense_mlp.cpp

xllm ILU kernels — synced 10 files to upstream (diffs from prior edits)

These are reference implementations, NOT hand-written.
Source repos: vllm-project/vllm, jd-opensource/xllm
 2026-08-15 14:26:24 +00:00
dylan
7aa5054574 feat: ILU kernel pipeline — ix_full_bridge_v2 build + deploy + 7-step MoE dispatch 
System design: algorithm factor replacement, not a connector.
All ops go through ixformer::infer C++ namespace (no Python fallback).

New files:
  build_ix_bridge.sh        — compile ix_full_bridge_v2.cpp on BI-V100
  build_xllm_ilu_kernels.sh — compile upstream xllm ILU wrappers
  deploy_ilu_pipeline.sh    — wire everything into patch_ops.sh
  ix_ops_dispatch.py        — runtime dispatcher (12 ops via C++ bridge)
  corex_fa2_dispatch.py     — 3-mode attention (prefill/v1/flash paged)
  fused_moe_ilu.py          — 7-step MoE pipeline (no expert for-loop)

Upstream sources used (not rewritten):
  xllm/core/kernels/ilu/*.cpp  (ILU kernel wrappers)
  xllm/core/kernels/ilu/ixformer.h (14 C++ function declarations)
  ds_vllm/csrc/libtorch_stable/*.cu (kernel references)

Call chain:
  patch_ops.sh → deploy_ilu_pipeline.sh → build_ix_bridge.sh
    → ix_full_bridge_v2.so → ixformer::infer::*
    → silu_and_mul, rms_norm, rotary_embedding, paged_attention,
      topk_softmax, group_gemm, expand_input, combine_result
 2026-08-15 14:15:47 +00:00
Claude
52e2ef31a8 feat: xllm_ops NO-FALLBACK kernel loader + 6 missing .so build targets + hot-path patcher 
Build infrastructure:
- build_xllm_kernels.sh: add 5 missing build targets (norm, rope, activation, cache, moe)
  Previously only built xllm_fused_qknorm_rope.so, now builds all 6 .so files

Kernel loader (xllm_ops.py):
- NO-FALLBACK architecture matching xllm/core/kernels/ilu/ dispatch chain
- Loads: xllm_norm.so, xllm_rope.so, xllm_activation.so, xllm_cache.so,
         xllm_moe.so, ix_full_bridge.so, xllm_fused_qknorm_rope.so
- check_all(strict=True) verifies ALL .so at startup

Hot-path patcher (patch_vllm_hot_path.py):
- Monkey-patches vllm._custom_ops to route through xllm .so
- Critical fix: topk_softmax patch prevents comp 168 cascade
- Patches: topk_softmax, rms_norm, silu_and_mul, rotary_embedding, reshape_and_cache

Source mapping: xllm/core/kernels/ilu/*.cpp -> our xllm_*.so files
 2026-08-15 14:13:13 +00:00
dylan
e873e5f27b fix: eliminate 8x CUDA sync in MoE decode — tolist() once instead of .item() per expert 2026-08-15 13:14:11 +00:00
dylan
23fe535985 fix: add ex_engine/__init__.py for Python package import 2026-08-15 13:08:24 +00:00
dylan
e18ece8f3a feat: port NaiveBatchedExperts from ds_vllm — view transpose + cublas transB 
Source: upstream_ref/ds_vllm/vllm/model_executor/layers/fused_moe/experts/fused_batched_moe.py
        upstream_ref/ds_vllm/vllm/model_executor/layers/fused_moe/activation.py

New files (ported from ds_vllm, adapted for BI-V100):
  ex_engine/moe/__init__.py
  ex_engine/moe/activation.py
    - MoEActivation enum + apply_moe_activation
    - torch.ops._C.silu_and_mul replaced with F.silu(gate)*up fallback
  ex_engine/moe/naive_batched_experts.py
    - naive_batched_moe_forward()
    - Decode: per-expert loop, w13[eid].transpose(0,1) is VIEW (zero copy)
    - @ operator → cublas passes transB=CUBLAS_OP_T internally
    - Prefill: group tokens by expert, batch @ per expert

Modified:
  qwen3_6_scripts/qwen3_5.py
    - Import naive_batched_moe_forward
    - Tier 0.5: after ix_fused_moe, before corex point-optimized loop
    - Uses existing topk routing (xllm/corex/pytorch)

Key difference from previous approach:
  - NO physical transpose (was 22ms overhead)
  - NO weight gather into contiguous buffer
  - View transpose is O(0), cublas handles transB
 2026-08-15 13:05:45 +00:00
dylan
e2fc3f270f fix: corex_batched_gemm use TCU OpClassTensorOp + Cu10 + float accum 
Previous version used default SIMT path (25ms).
Fixed version matches moe_cutlass_batched.cu (2.462ms):
  - ElementAccumulator = float (was half_t)
  - OpClassTensorOp (was default OpClassSimt)
  - arch::Cu10 (was default Sm61)
  - RowMajor layout (was ColumnMajor)
  - torch::sigmoid(x)*x instead of torch::silu (not in corex torch)

Also fixed bind.cpp: removed col-major transposition logic,
kernel now RowMajor so A(M,K) @ B(K,N) = C(M,N) directly.
 2026-08-15 12:35:56 +00:00
dylan
ddcfbad431 feat: pybind wrapper for CUTLASS batched GEMM → MoE decode path 
Based on verified result (issue #68):
  CUTLASS Cu10 TensorOp batched: 2.462ms (8 experts, 1 launch)
  vs 8× torch.matmul: 4.6ms (8 launches)
  vs Python F.linear loop: 10.36ms

New files:
  ex_engine/xllm_kernels/cuda/bindings/corex_batched_gemm_bind.cpp
    pybind11 wrapper: batched_gemm_fp16() + moe_decode_fused()
  ex_engine/xllm_kernels/cuda/corex_batched_gemm_kernel.cu
    CUTLASS GemmBatched<half> kernel (from cat_files/batched_gemm.cu)
  qwen3_6_scripts/build_corex_batched_gemm.sh
    Build script for BI-V100 (ivcore10)

Modified:
  qwen3_6_scripts/qwen3_5.py
    import corex_batched_gemm + _USE_COREX_BATCHED_GEMM flag
    Tier 1.5 in MoE decode: after corex_direct_routed, before corex_gather

Build on device: bash qwen3_6_scripts/build_corex_batched_gemm.sh
Output: prebuilt/corex-3.2.3-ivcore10/corex_batched_gemm.so
 2026-08-15 11:54:26 +00:00
Claude
36676f2d1b data: complete SGEMM upstream from 3 repos (siboehm+wangzyon+edtallison) + xllm fused_qknorm_rope + xattention kernels 
SGEMM repos (upstream_ref/sgemm_cuda/, 41 files):
  siboehm/SGEMM_CUDA: kernel 1-12, runner, CMake, cuBLAS benchmark
  wangzyon/NVIDIA_SGEMM_PRACTICE: kernel 1-7 (Chinese comments), utils
  edtallison/sgemm-cuda: kernel 01-09 (learning notes), Makefile

xllm kernels (ex_engine/xllm_kernels/cuda/):
  fused_qknorm_rope.cu + bind — saves 128 kernel launches/fwd
  xattention/ — 6 files from upstream xllm
  headers: corex_compat_utils.h, topk_last_dim.cuh
  ilu/CMakeLists.txt

SO_BUILD_MANIFEST.md — complete .so inventory and call chain analysis
 2026-08-15 07:00:09 +00:00
dylan
e8f0948fe1 feat: ix_ops integration layer — wire ix_full_bridge.so into vllm hot path 
Architecture (CCCL dispatch pattern):
  base_image ixformer::infer → ix_full_bridge.so → ix_ops.py → vllm patches

New files:
  ex_engine/python/ix_ops.py          — Python API for all 14 ixformer::infer ops
  ex_engine/python/patch_vllm_ops.py  — monkey-patch vllm GemmaRMSNorm, SiluAndMul
  ex_engine/deploy_ix_bridge.sh       — build-time deployment script

Modified:
  qwen3_6_scripts/patch_ops.sh        — integrated ix_bridge deployment + startup hook

Call chain: DecoderLayer.forward → GemmaRMSNorm → ix_ops.fused_add_rms_norm
            → ixformer::infer::residual_rms_norm (fused C++ kernel)
 2026-08-15 06:15:17 +00:00
Claude
045ea5df79 feat: Cu10 TensorOp batched HGEMM via Iluvatar CUTLASS framework 
From corex-samples batched_gemm.cu, changed:
  float → half_t, OpClassSimt → OpClassTensorOp, Sm61 → Cu10
Uses __ivcorex_matrix_mad_f32x4_f16x4 via mma_cu10.h
Default config: TB<128,128,32> Warp<32,32,32> Inst<16,16,16>

Standalone test: correctness + perf for MoE decode (8 × 1x4096@4096x11008)
 2026-08-15 05:44:15 +00:00
Claude
a465dd1d75 fix: use F.silu in test script for old corex torch 2026-08-15 05:22:31 +00:00
Claude
a12d070d82 fix: replace torch::silu with x*sigmoid(x) for old corex torch 2026-08-15 05:22:25 +00:00
Claude
c840c9159f feat: moe_tcu_dispatch.cpp — C++ MoE expert loop via torch::mm (TCU kernel) 
torch profiler confirmed: torch.mm launches Gemm_tcu_bi_kernel::gemm_h_h_tcu_25
which is BI-V100 TCU (Tensor Compute Unit) hardware-accelerated GEMM.
0.58ms per call vs our custom kernel 7.7ms — TCU is 13x faster.

Python for-loop overhead measured: 0.892 ms/expert = 7.1 ms for 8 experts.
This C++ dispatch eliminates that overhead while using the same TCU kernel.

Three entry points:
- moe_decode: full MoE forward (FC1 + SiLU*mul + FC2) for decode
- moe_prefill: group-by-expert MoE forward for prefill
- moe_expert_gemm_tcu: raw GEMM loop for benchmarking
 2026-08-15 05:20:05 +00:00
Claude
395b3e4042 test: clean rebuild + debug output for kernel 10 correctness 2026-08-15 05:14:18 +00:00
Claude
a8ca42b59c perf: hgemm_warptiling Config B — beats cublas on MoE-sized GEMM (0.7x) 
probe_k10_configs.sh results on BI-V100:
  256x4096 @ 4096x11008:
    cublas:   10.554 ms
    Config B:  7.649 ms (0.7x cublas — FASTER)
    Config A:  2308 ms  (old broken config)

Config B: BM128 BN128 BK16 WM64 WN64 WNITER2 TM8 TN4 NT128
Root cause of Config A slowness: WN=128 WNITER=4 caused
excessive register pressure and smem bank conflicts.
 2026-08-15 05:11:32 +00:00
Claude
2b12fe687e feat: hgemm_warptiling.cu — siboehm kernel 10 ported to WARPSIZE=64 FP16 
1:1 from upstream_ref/sgemm_cuda/10_kernel_warptiling.cuh.
3 changes: WARPSIZE 32→64, float→__half, FP32 accumulator.

Launch config (confirmed by probe_warp64.sh):
  NUM_THREADS=128, 2 warps of 64
  BM=128 BN=128 BK=16 WM=64 WN=128 WNITER=4 TM=4 TN=4
  WMITER=2, WSUBM=32, WSUBN=32, threads_per_warp=64 ✓
 2026-08-14 17:05:59 +00:00
Claude
1af7e7cf48 fix: use c10::cuda::getCurrentCUDAStream().stream() for corex torch 2026-08-14 16:49:47 +00:00
Claude
3bee73207e fix: add cuda_runtime.h to hgemm_bind.cpp for cudaStream_t 2026-08-14 16:33:29 +00:00
Claude
09e5261ba6 refactor: hgemm_blocktiling.cu — strict 1:1 from siboehm kernel 6 
Only 3 changes from upstream_ref/sgemm_cuda/6_kernel_vectorize.cuh:
1. float → __half for A/B/C data and shared memory
2. float4 vectorized load → 4 scalar half loads (float4 needs 16-byte align)
3. threadResults accumulator stays float (FP32 accumulation)

Everything else identical: same shared mem layout, same indexing,
same A-transpose-while-loading, same thread tile computation.
No WARPSIZE. No cooperative_groups. No cuda::barrier.
 2026-08-14 16:24:22 +00:00
Claude
ab42fc1fd7 feat: hgemm_blocktiling.cu — FP16 GEMM kernel for MoE expert dispatch on BI-V100 
Adapted from siboehm/SGEMM_CUDA kernel 6 (vectorize + A transpose)
and wangzyon/NVIDIA_SGEMM_PRACTICE kernel 6 (mysgemm_v6).

Key design decisions:
- FP16 data with FP32 accumulation (avoid precision loss)
- No WARPSIZE dependency (safe for BI-V100 warp_size=64)
- Boundary checks for non-aligned M/N/K (MoE expert token counts vary)
- BM=128 BN=128 BK=8 TM=8 TN=8 (256 threads, fits BI-V100 128KB smem)
- A transpose in shared memory for coalesced reads

Two entry points:
1. hgemm(A, B) — standalone FP16 GEMM
2. moe_expert_gemm(input, weights, expert_counts) — MoE prefill path
   loops over experts with variable token counts

For decode (M=1), use cublasHgemmStridedBatched (confirmed working).

Upstream refs: upstream_ref/sgemm_cuda/6_kernel_vectorize.cuh
              upstream_ref/nvidia_sgemm_practice/kernel_6.cuh
 2026-08-14 16:22:00 +00:00
Claude
29ecc2e602 feat: moe_expert_gemm.cpp — C++ loop over experts via ixformer_linear (replaces Python for-loop) 
Key difference from the reverted batched approach:
- Does NOT use torch::mm in a C++ loop (that was the reverted commit)
- Uses ixformer_torch_ext::ixformer_linear — the base image's optimized GEMM
- Same kernel the competitor (sub 168) uses via corex_moe.py
- Eliminates Python interpreter + dispatcher overhead per expert
- Links against _ixformer_torch.cpython-310.so (already in base image)

Decode: 1 Python call → 8 C++ ixformer_linear (vs 8 Python F.linear)
Prefill: 1 Python call → 64 C++ ixformer_linear (vs 64 Python F.linear)
 2026-08-14 12:09:50 +00:00
claude
50a249e0a3 Revert "feat: batched MoE expert GEMM — replaces Python for-loop" 
This reverts commit 06d7713db6.
 2026-08-14 11:47:37 +00:00
claude
06d7713db6 feat: batched MoE expert GEMM — replaces Python for-loop 
ixformer probe results:
  ✗ moe_w16a16_group_gemm NOT in ixformer .so
  ✗ CUTLASS grouped GEMM needs cuda/std (variadic function error on corex)
  ✓ ixformer_linear EXISTS (fused matmul)
  ✓ torch.mm works (uses corex cublas)

Solution: moe_batched_gemm.cu
  - C++ loop over experts (eliminates Python overhead)
  - torch::mm for GEMM (corex cublas, not F.linear Python)
  - Fused silu_and_mul CUDA kernel (not PyTorch ops)
  - Weighted scatter-add in C++
  - Skips empty experts (no wasted compute)

Integration in qwen3_5.py:
  _USE_XLLM_MOE_GEMM dispatches to moe_experts_forward()
  Falls back to Python for-loop if not available

Build: bash qwen3_6_scripts/build_xllm_kernels.sh
 2026-08-14 11:43:46 +00:00
claude
31d3ee99bb fix: MoE kernel include paths — device_utils.cuh + arch_condition.h 
Fixed xllm internal paths to our headers/ directory:
  kernels/cuda/device_utils.cuh → device_utils.cuh
  core/kernels/cuda/device_utils.cuh → device_utils.cuh
  core/kernels/cuda/arch_condition.h → arch_condition.h (copied)
 2026-08-14 11:31:54 +00:00
claude
df6a0f5d47 fix: remove cuda/functional from MoE topk kernels (not available on corex) 2026-08-14 11:29:19 +00:00
claude
a50adefdfc feat: xllm MoE CUDA kernels — fused_topk + compute_index + combine 
3 MoE kernel files adapted for corex:
  moe_fused_topk.cu: LOG(FATAL)→TORCH_CHECK, +torch/extension.h
  moe_compute_index.cu: CHECK_LE→TORCH_CHECK, uses cub::BlockScan (corex CUB)
  moe_combine.cu: fixed duplicate include, +torch/extension.h

New pybind binding: xllm_moe_bind.cpp
  → moe_fused_topk(gating, topk, renormalize, bias, scoring_func)
  → moe_compute_index(expert_id, num_experts)
  → moe_combine_result(gemm2, weights, N, topk)

AST verification added for all 3 functions
 2026-08-14 11:23:49 +00:00
claude
3d816cd18d fix: add ceil_div + DEVICE_INLINE to device_utils.cuh 
ceil_div<T> was in xllm utils.h (removed for glog).
DEVICE_INLINE macro also moved to shared header.
 2026-08-14 11:11:15 +00:00
claude
302aa9608a fix: block_copy.cu — DEVICE_INLINE, CHECK_EQ→TORCH_CHECK, cstdint 
Remaining glog dependencies removed:
  - DEVICE_INLINE macro defined inline
  - CHECK_EQ(a,b) → TORCH_CHECK(a == b)
  - CHECK_GT(a,b) → TORCH_CHECK(a > b)
  - #include <cstdint> for int32_t
 2026-08-14 11:06:07 +00:00
claude
900ae0b1ef fix: block_copy.cu remove utils.h (glog), CHECK→TORCH_CHECK 
3/4 kernels now compile:
  ✓ xllm_norm.so      (rms_norm, fused_add_rms_norm)
  ✓ xllm_activation.so (silu_and_mul, gelu_and_mul, act_and_mul)
  ✓ xllm_rope.so       (rotary_embedding)
  → xllm_cache.so      block_copy.cu had utils.h→glog — fixed
 2026-08-14 11:02:57 +00:00