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Model: mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF Source: Original Platform
2026-05-10 02:30:17 +08:00
commit 7e7dbfb898
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--- a/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.f16.gguf
+++ b/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.f16.gguf
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
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