mradermacher/Qwen-2.5-Instruct-Verilog-Reasoning-7B-GGUF
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2026-05-08 22:28:06 +08:00
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version https://git-lfs.github.com/spec/v1
oid sha256:acad8ccca22dea6f5094f84a06dcbe564575673833eae5b5b959974832025992
size 4457769408