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  • fee8f1b9e4 docs: document Qwen3.6-35B-A3B bootstrap failure and architecture analysis Claude 2026-08-01 13:16:01 +00:00
  • 9b0d1c283c docs: add competition server profile (4×BI-V100, Qwen3.6-35B-A3B) Claude 2026-08-01 13:12:59 +00:00
  • 79730ea907 test: add SMEM safety validator for all 26 tuning algorithms dylanyunlon 2026-08-01 12:37:14 +08:00
  • 0154a3b297 fix(tuning_batched_topk): force bits=8, fix SMEM overflow dylanyunlon 2026-08-01 12:36:57 +08:00
  • 2c5e77f370 feat(gen_patch): add TUNING_REGISTRY for all 26 algorithms dylanyunlon 2026-08-01 12:33:14 +08:00
  • 84c18150e6 fix(tuning_select_if): restore 3 collapsed dispatch dimensions dylanyunlon 2026-08-01 02:26:48 +08:00
  • 9287700964 fix(tuning_radix_sort): remove invented portioned_smem_per_warp field dylanyunlon 2026-08-01 02:26:46 +08:00
  • 2bc3263793 [muh] add tuning_radix_sort.cuh: BI-V100 tuning for radix_sort dylanyunlon 2026-08-01 02:11:05 +08:00
  • 437fc3ea20 [muh] add tuning_unique_by_key.cuh: BI-V100 tuning for unique_by_key dylanyunlon 2026-08-01 02:11:03 +08:00
  • 58de86d817 [muh] add tuning_select_if.cuh: BI-V100 tuning for select_if dylanyunlon 2026-08-01 02:11:01 +08:00
  • 91f9a3a0e5 [muh] add tuning_scan_by_key.cuh: BI-V100 tuning for scan_by_key dylanyunlon 2026-08-01 02:10:59 +08:00
  • 0ec355cf74 [muh] add tuning_reduce_by_key.cuh: BI-V100 tuning for reduce_by_key dylanyunlon 2026-08-01 02:10:57 +08:00
  • 915c4aff56 [muh] add tuning_segmented_sort.cuh: BI-V100 tuning for segmented_sort dylanyunlon 2026-08-01 02:10:55 +08:00
  • 561a82c849 [muh] add tuning_three_way_partition.cuh: BI-V100 tuning for three_way_partition dylanyunlon 2026-08-01 02:10:54 +08:00
  • aeb270578f [muh] add tuning_rle_non_trivial_runs.cuh: BI-V100 tuning for rle_non_trivial_runs dylanyunlon 2026-08-01 02:10:52 +08:00
  • f3ae28bbb5 [muh] add tuning_rle_encode.cuh: BI-V100 tuning for rle_encode dylanyunlon 2026-08-01 02:10:50 +08:00
  • f838c22bad [muh] add tuning_histogram.cuh: BI-V100 tuning for histogram dylanyunlon 2026-08-01 02:10:48 +08:00
  • 3a8030224b [muh] add tuning_segmented_radix_sort.cuh: BI-V100 tuning header for segmented_radix_sort dylanyunlon 2026-08-01 02:08:44 +08:00
  • c3e9e5b6f5 [muh] add tuning_batched_topk.cuh: BI-V100 tuning header for batched_topk dylanyunlon 2026-08-01 02:08:42 +08:00
  • 0344a3fbb8 [muh] add tuning_transform_tile.cuh: BI-V100 tuning header for transform_tile dylanyunlon 2026-08-01 02:08:40 +08:00
  • 3fee54f4d7 [muh] add tuning_merge_sort.cuh: BI-V100 tuning header for merge_sort dylanyunlon 2026-08-01 02:08:38 +08:00
  • af8fc0caeb [muh] add tuning_merge.cuh: BI-V100 tuning header for merge dylanyunlon 2026-08-01 02:08:37 +08:00
  • c0bfc8c93d [muh] add tuning_segmented_scan.cuh: BI-V100 tuning header for segmented_scan dylanyunlon 2026-08-01 02:08:35 +08:00
  • 105dd96b52 [muh] add tuning_segmented_reduce.cuh: BI-V100 tuning header for segmented_reduce dylanyunlon 2026-08-01 02:08:33 +08:00
  • 81e4a907c0 [muh] add tuning_find_bound_sorted_values.cuh: BI-V100 tuning header for find_bound_sorted_values dylanyunlon 2026-08-01 02:08:31 +08:00
  • 25f7a636a9 [muh] add tuning_find.cuh: BI-V100 tuning header for find dylanyunlon 2026-08-01 02:08:29 +08:00
  • eaca73a390 [muh] add tuning_adjacent_difference.cuh: BI-V100 tuning header for adjacent_difference dylanyunlon 2026-08-01 02:08:28 +08:00
  • 52c5ca7ce5 refactor(muh_dispatch): read-once from C++ headers, not write-twice dylanyunlon 2026-08-01 01:30:42 +08:00
  • 482aabdea3 fix(muh_kernel_map): add threads >= 32 floor in Python scale_mem_bound dylanyunlon 2026-08-01 01:29:57 +08:00
  • 142568072a fix(common.cuh): add threads >= 32 floor in scale_mem_bound dylanyunlon 2026-08-01 01:29:47 +08:00
  • 03f6a59ebf fix(muh_dispatch): add verify_against_headers() to close the loop dylanyunlon 2026-08-01 00:32:16 +08:00
  • 3a2b67c166 fix(tuning_reduce): auto [t,i] → auto [i,t] matching CCCL scaling_result dylanyunlon 2026-08-01 00:31:41 +08:00
  • ec1c85cd9a fix(common.cuh): scale_mem_bound — 3 bugs vs CCCL original dylanyunlon 2026-08-01 00:31:22 +08:00
  • 3ebc37d80d [muh] fix scale_mem_bound: 3 bugs vs CCCL util_arch.cuh dylanyunlon 2026-08-01 00:00:02 +08:00
  • 173c6afe09 [muh] kernel_map: full vllm→CCCL mapping with SMEM overflow detection Claude 2026-07-31 11:13:33 +00:00
  • e69c46d0b7 [muh] add muh_dispatch.py — CCCL-style type-dispatched kernel config for BI-V100 dylanyunlon 2026-07-31 19:11:46 +08:00
  • d14b0c19e4 [docs] add CCCL SM100 vs muh BI-V100 specialization parity analysis dylanyunlon 2026-07-31 18:35:50 +08:00
  • 35ef79c5f8 [muh] scan: add bi100_lookback_1B_o8 — close SM100 parity gap (7/7 lookback branches) dylanyunlon 2026-07-31 18:35:01 +08:00
  • c5a0d61851 sync: align with enginex-vllm-bi100-qwen36 baseline (1902c81f) Claude 2026-07-31 09:43:58 +00:00
  • de7ee4383e [VERIFIED] Hardware-tested native kernel integration Claude 2026-07-31 06:43:25 +00:00
  • 78a0ebd516 [CRITICAL] Fix V2 cache layout: V1=5D K, V2=4D K with transposed layout Claude 2026-07-31 06:33:06 +00:00
  • 4867d4f780 [CRITICAL] Enable ixformer native V1/V2 paged attention kernels Claude 2026-07-31 06:18:32 +00:00
  • 39e32343eb [ARCH] CCCL-derived paged attention kernel architecture + Triton rewrite Claude 2026-07-31 04:13:07 +00:00
  • 2316199c97 [FIX] V2 shape mismatch bug — v_padded used num_heads for kv_h tensor Claude 2026-07-31 03:52:23 +00:00
  • cd0d9e1a91 [OPT] Fix online softmax bug in Triton V2 Phase 1 Claude 2026-07-30 16:16:56 +00:00
  • d9bbef54d8 [OPT] Complete GQA broadcast — V weighted sum also avoids expansion Claude 2026-07-30 16:15:34 +00:00
  • 8951d74936 [OPT] Raise max-seq-len-to-capture to 65536 for more CUDA graph coverage dylanyunlon 2026-07-30 16:14:57 +00:00
  • 0c60ed8784 [OPT] GQA broadcast in V2 — eliminate 1GB/step memory allocation Claude 2026-07-30 16:13:54 +00:00
  • 7ad59e781f [OPT] MoE prefill: sorted-token grouped GEMM (contiguous per-expert access) dylanyunlon 2026-07-30 16:12:38 +00:00
  • 33f6ead1b8 [OPT] Complete Triton V2 Phase 1 — paged K/V gather from prefix_prefill.py pattern Claude 2026-07-30 16:07:09 +00:00
  • ef6abf3dc7 [DEPLOY] Complete submission: baseline + all optimizations dylanyunlon 2026-07-30 16:06:20 +00:00
  • 3722503dee [OPT] Optimized paged_attn.py: pre-gather context KV + V2 heuristic + Triton fallback dylanyunlon 2026-07-30 16:05:04 +00:00
  • 6d8de852ad [OPT] head_dim=256 Triton support — BLOCK=32 for Qwen3.6 Claude 2026-07-30 16:05:01 +00:00
  • a53d1a28b0 [OPT] Triton paged_attention_v2 kernel skeleton — Phase 2 reduction complete Claude 2026-07-30 15:59:12 +00:00
  • cbe6066257 [OPT] V2 single-bmm: 195 kernel launches → 3 (CCCL transform_reduce pattern) dylanyunlon 2026-07-30 15:58:26 +00:00
  • 15ef28e863 [OPT] Vectorize paged_attention_v2 — eliminate block-gather for-loop dylanyunlon 2026-07-30 15:44:46 +00:00
  • 638858a317 [OPT] Enable Triton prefill + raise decode threshold — the actual performance work dylanyunlon 2026-07-30 15:41:01 +00:00
  • 9cb7f9d037 [OPT] PagedAttention V2 implementation — fill the NotImplementedError hole Claude 2026-07-30 15:40:14 +00:00
  • 4463e9ccee [OPT] BI-V100 Triton kernel tuning + computility-run.yaml optimization Claude 2026-07-30 15:33:44 +00:00
  • c6e298831f update baseline dylanyunlong 2026-07-30 15:19:37 +00:00
  • 4c796fe4b3 [MUH] Derive BI-V100 tuning values from hardware specs — fix 5 SMEM overflow bugs Claude 2026-07-30 15:08:30 +00:00
  • c7a63bc2c8 [MUH] Fix 7 structural discrepancies vs CCCL — read source, not grep Claude 2026-07-30 14:37:38 +00:00
  • e02134a3ce [MUH] Delete 20 dead-code batch-generated tuning headers dylanyunlon 2026-07-30 14:22:18 +00:00
  • 07b015f31e [MUH] Complete all 26 CCCL algorithm tuning headers — full parity with cub/device/dispatch/tuning/ Claude 2026-07-30 14:19:51 +00:00
  • 57e222b99d [MUH] Fix three-layer disconnect — C++ headers are now the single source of truth dylanyunlon 2026-07-30 14:12:33 +00:00
  • 5f880bb279 [MUH] Add C++/CUDA tuning headers — the real muh, not Python wrappers dylanyunlon 2026-07-30 14:01:07 +00:00
  • 9b21a13119 [MUH] Bootstrap muh toolchain — extract/parse/gen_yaml/gen_patch + baseline.muh dylanyunlon 2026-07-30 10:39:06 +00:00
  • 70e80c5810 [DOC] Append CCCL tuning analysis to checkpoint — all 27 files consumed as model input EngineX CI 2026-07-30 10:30:36 +00:00
  • e7fdf5777a [DOC] Add MUH project checkpoint — single source of truth for context continuity EngineX CI 2026-07-30 09:59:15 +00:00
  • 56fd68e7dd [INFRA] Import NVIDIA/CCCL upstream as optimization reference library EngineX CI 2026-07-30 09:35:51 +00:00
  • b4d01f481e Initial commit dylanyunlon 2026-07-30 17:03:23 +08:00