56fd68e7dd
CCCL (CUDA C++ Core Libraries) provides: - CUB: device/block/warp-level GPU primitives (reduce, scan, sort, topk) - Thrust: high-level parallel algorithms (transform_reduce, sort, scan) - libcudacxx: CUDA C++ standard library (atomics, barriers, memory) - cudax: experimental features (memory resources, allocators) - Tuning policies: per-SM hardware-specific algorithm parameters Competition optimization vectors mapped to CCCL: - Output TPS (83% weight): warp_reduce, block_reduce, device_topk - Input TPS (14% weight): device_scan, block_load, prefetch - Cache TPS (3% weight): prefix caching strategy patterns - Memory (0.9 util): pooled/cached/buddy allocators Source: https://github.com/NVIDIA/cccl (shallow clone, HEAD only) License: Apache-2.0
72 lines
2.3 KiB
Plaintext
72 lines
2.3 KiB
Plaintext
// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION. All rights reserved.
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// SPDX-License-Identifier: BSD-3
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#include <thrust/device_vector.h>
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#include <thrust/execution_policy.h>
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#include <thrust/sequence.h>
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#include <thrust/tabulate.h>
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#include <nvbench_helper.cuh>
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#include "thrust/detail/raw_pointer_cast.h"
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template <typename T>
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static void sequence(nvbench::state& state, nvbench::type_list<T>)
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{
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const auto elements = static_cast<std::size_t>(state.get_int64("Elements"));
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thrust::device_vector<T> output(elements, thrust::no_init);
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state.add_element_count(elements);
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state.add_global_memory_writes<T>(elements);
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caching_allocator_t alloc;
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state.exec(nvbench::exec_tag::gpu | nvbench::exec_tag::no_batch | nvbench::exec_tag::sync,
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[&](nvbench::launch& launch) {
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// sequence is implemented via thrust::tabulate
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thrust::sequence(policy(alloc, launch), output.begin(), output.end());
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});
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}
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NVBENCH_BENCH_TYPES(sequence, NVBENCH_TYPE_AXES(integral_types))
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.set_name("sequence")
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.set_type_axes_names({"T{ct}"})
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.add_int64_power_of_two_axis("Elements", nvbench::range(16, 28, 4));
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template <class T>
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struct seg_size_t
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{
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T* d_offsets{};
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template <class OffsetT>
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__device__ T operator()(OffsetT i)
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{
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return static_cast<T>(d_offsets[i + 1] - d_offsets[i]);
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}
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};
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template <typename T>
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static void seg_size(nvbench::state& state, nvbench::type_list<T>)
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{
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const auto elements = static_cast<std::size_t>(state.get_int64("Elements"));
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thrust::device_vector<T> input(elements + 1);
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thrust::device_vector<T> output(elements, thrust::no_init);
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state.add_element_count(elements);
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state.add_global_memory_reads<T>(elements + 1);
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state.add_global_memory_writes<T>(elements);
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caching_allocator_t alloc;
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seg_size_t<T> op{thrust::raw_pointer_cast(input.data())};
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state.exec(nvbench::exec_tag::gpu | nvbench::exec_tag::no_batch | nvbench::exec_tag::sync,
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[&](nvbench::launch& launch) {
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thrust::tabulate(policy(alloc, launch), output.begin(), output.end(), op);
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});
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}
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NVBENCH_BENCH_TYPES(seg_size, NVBENCH_TYPE_AXES(integral_types))
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.set_name("seg_size")
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.set_type_axes_names({"T{ct}"})
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.add_int64_power_of_two_axis("Elements", nvbench::range(16, 28, 4));
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