// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION. All rights reserved. // SPDX-License-Identifier: BSD-3 #include #include #include #include #include #include "thrust/detail/raw_pointer_cast.h" template static void sequence(nvbench::state& state, nvbench::type_list) { const auto elements = static_cast(state.get_int64("Elements")); thrust::device_vector output(elements, thrust::no_init); state.add_element_count(elements); state.add_global_memory_writes(elements); caching_allocator_t alloc; state.exec(nvbench::exec_tag::gpu | nvbench::exec_tag::no_batch | nvbench::exec_tag::sync, [&](nvbench::launch& launch) { // sequence is implemented via thrust::tabulate thrust::sequence(policy(alloc, launch), output.begin(), output.end()); }); } NVBENCH_BENCH_TYPES(sequence, NVBENCH_TYPE_AXES(integral_types)) .set_name("sequence") .set_type_axes_names({"T{ct}"}) .add_int64_power_of_two_axis("Elements", nvbench::range(16, 28, 4)); template struct seg_size_t { T* d_offsets{}; template __device__ T operator()(OffsetT i) { return static_cast(d_offsets[i + 1] - d_offsets[i]); } }; template static void seg_size(nvbench::state& state, nvbench::type_list) { const auto elements = static_cast(state.get_int64("Elements")); thrust::device_vector input(elements + 1); thrust::device_vector output(elements, thrust::no_init); state.add_element_count(elements); state.add_global_memory_reads(elements + 1); state.add_global_memory_writes(elements); caching_allocator_t alloc; seg_size_t op{thrust::raw_pointer_cast(input.data())}; state.exec(nvbench::exec_tag::gpu | nvbench::exec_tag::no_batch | nvbench::exec_tag::sync, [&](nvbench::launch& launch) { thrust::tabulate(policy(alloc, launch), output.begin(), output.end(), op); }); } NVBENCH_BENCH_TYPES(seg_size, NVBENCH_TYPE_AXES(integral_types)) .set_name("seg_size") .set_type_axes_names({"T{ct}"}) .add_int64_power_of_two_axis("Elements", nvbench::range(16, 28, 4));