project6-dev 905bf4db2c feat(moe): wire silu_and_mul through C++ bridge in corex_moe.py ...

Now MoE activation uses:
  Tier 0: ix_bridge.silu_and_mul (C++ ixformer_torch_ext, verified on BI-V100)
  Tier 1: ixformer.functions.silu_and_mul (Python)
  Tier 2: F.silu(gate) * up (pure PyTorch)

Verified 7/8 on single BI-V100:
  ✓ compile, silu_and_mul, rms_norm, fused_add_rms_norm, linear, paged_attn, corex_moe
  ✗ flash_attn import path (not needed, vllm xformers backend handles it)

2026-08-10 06:36:40 +00:00

..

__init__.py

feat(EX): Algorithm Factor Replacement Engine — dlopen-based CUDA kernel dispatch

2026-08-10 02:25:23 +00:00

corex_fa2.py

refactor(corex): rewrite 3 dlopen modules to use real ixformer::infer dispatch chain

2026-08-10 06:16:39 +00:00

corex_gdn.py

refactor(corex): rewrite 3 dlopen modules to use real ixformer::infer dispatch chain

2026-08-10 06:16:39 +00:00

corex_moe.py

feat(moe): wire silu_and_mul through C++ bridge in corex_moe.py

2026-08-10 06:36:40 +00:00

ex_loader.py

fix(EX): corex ivcore10 build flags + deploy pipeline + topk kernel cleanup

2026-08-10 02:31:55 +00:00

ix_bridge.py

fix(bridge): link against libixformer.so for silu_and_mul symbol

2026-08-10 06:29:11 +00:00

moe_topk.py

feat(EX): wire xllm CUB topk_softmax kernel into MoE routing

2026-08-10 03:10:58 +00:00

patch_model.py

refactor(EX): upstream-aligned kernels + FlashQLA GDN backend

2026-08-10 02:55:58 +00:00