5c05a03470
gen_config.py replaces gen_patch.py's dead csrc/*.cu injection path. Generates Triton autotune configs derived from CCCL tuning principles: - SMEM constraints (Q_tile + K_tile <= 48KB for head_dim=256) - Occupancy model (16 SMs, register pressure per config) - bytes_in_flight (56 GB/s per-SM -> 64KB -> num_stages=2) 63 valid configs from 2304 combinations, 19 new. PIPELINE_REALITY_CHECK.md: enginex has no .cu source. All injection targets are Python/Triton, not C++.
352 lines
14 KiB
Python
352 lines
14 KiB
Python
#!/usr/bin/env python3
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"""muh/gen_config.py — Generate Python-layer config patches from CCCL tuning analysis
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Unlike gen_patch.py (which targets non-existent .cu files), this generates
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patches for the ACTUAL tunable parameters in enginex-vllm-bi100:
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1. paged_attn.py: _PARTITION_SIZE, V1/V2 dispatch
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2. prefix_prefill.py: BLOCK, BLOCK_N, NUM_WARPS
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3. triton_flash_attention.py: autotune Config entries
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4. _custom_ops.py: SMEM size
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5. computility-run.yaml: scheduler params
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Each config is derived from CCCL tuning principles (SMEM constraints,
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occupancy model, bytes_in_flight) applied to BI-V100 hardware.
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"""
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import os
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import sys
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import json
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import math
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from dataclasses import dataclass, field
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from typing import List, Dict, Optional, Tuple
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# BI-V100 hardware (from hardware.cuh, confirmed via ixsmi)
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HW = {
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"sm_count": 16,
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"smem_per_block": 49152, # 48KB
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"l2_cache_bytes": 6 * 1024 * 1024, # 6MB
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"hbm_bw_gbps": 900,
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"warp_size": 32,
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"max_threads_per_block": 1024,
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"max_regs_per_thread": 255,
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"regs_per_sm": 65536,
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# Derived
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"bw_per_sm_gbps": 900 / 16, # 56.25 GB/s
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# bytes_in_flight = BW/SM × memory_latency ≈ 56 × 1100ns ≈ 62KB → 64KB
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"bytes_in_flight": 64 * 1024,
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# L2 per SM = 6MB / 16 = 384KB (higher than SM100's 338KB/SM!)
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"l2_per_sm_bytes": 6 * 1024 * 1024 // 16,
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}
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# Qwen3.6-35B-A3B model config
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MODEL = {
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"head_dim": 256, # CONFIRMED from qwen3_5.py
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"num_q_heads": 28, # num_attention_heads
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"num_kv_heads": 4, # num_key_value_heads
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"hidden_size": 3584,
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"intermediate_size": 18944,
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"num_layers": 64,
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"vocab_size": 152064,
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"num_experts": 256, # MoE
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"top_k_experts": 8,
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"max_model_len": 100000,
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}
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@dataclass
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class TritonConfig:
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block_m: int
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block_n: int
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num_warps: int
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num_stages: int
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pre_load_v: bool = False
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waves_per_eu: int = 2
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def smem_bytes(self, head_dim: int, elem_size: int) -> int:
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"""SMEM = Q_tile + K_tile + V_tile + softmax_accum"""
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q_tile = self.block_m * head_dim * elem_size
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k_tile = head_dim * self.block_n * elem_size
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# V loaded in inner loop, not staged simultaneously with Q+K
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# But PRE_LOAD_V stages V in registers, not SMEM
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softmax = self.block_m * 4 * 2 # m_i + l_i, fp32
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return q_tile + k_tile + softmax
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def fits_smem(self, head_dim: int = 256, elem_size: int = 2) -> bool:
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return self.smem_bytes(head_dim, elem_size) <= HW["smem_per_block"]
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def occupancy_ctas(self, head_dim: int = 256, elem_size: int = 2) -> int:
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"""Max concurrent CTAs per SM"""
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threads = self.num_warps * HW["warp_size"]
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smem = self.smem_bytes(head_dim, elem_size) * self.num_stages
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# Thread limit
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ctas_by_threads = HW["max_threads_per_block"] // threads
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# SMEM limit
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ctas_by_smem = HW["smem_per_block"] // max(1, smem)
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# Register limit (rough: assume 40 regs/thread)
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regs_per_cta = threads * 40
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ctas_by_regs = HW["regs_per_sm"] // max(1, regs_per_cta)
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return min(ctas_by_threads, ctas_by_smem, ctas_by_regs)
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def to_triton_str(self) -> str:
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return (
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f'triton.Config({{"BLOCK_M": {self.block_m}, "BLOCK_N": {self.block_n}, '
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f'"waves_per_eu": {self.waves_per_eu}, "PRE_LOAD_V": {self.pre_load_v}}}, '
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f'num_stages={self.num_stages}, num_warps={self.num_warps})'
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)
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def generate_triton_configs(
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head_dim: int = 256,
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elem_size: int = 2, # bf16/fp16
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) -> List[TritonConfig]:
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"""Generate all valid BI-V100 Triton flash attention configs.
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CCCL-derived constraints:
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- SMEM: Q_tile + K_tile + softmax ≤ 48KB
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- Occupancy: want ≥2 CTAs/SM for 16 SMs
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- bytes_in_flight: num_stages=2 matches 64KB BIF sweet spot
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- Wave efficiency: total CTAs should be multiple of 16
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"""
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configs = []
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for block_m in [16, 32, 64, 128]:
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for block_n in [16, 32, 64, 128]:
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for num_warps in [2, 4, 8]:
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for num_stages in [1, 2]:
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for pre_load_v in [False, True]:
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for waves in [1, 2, 4]:
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cfg = TritonConfig(
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block_m=block_m,
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block_n=block_n,
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num_warps=num_warps,
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num_stages=num_stages,
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pre_load_v=pre_load_v,
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waves_per_eu=waves,
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)
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# Filter 1: SMEM must fit
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if not cfg.fits_smem(head_dim, elem_size):
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continue
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# Filter 2: threads must be reasonable
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threads = num_warps * 32
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if threads > HW["max_threads_per_block"]:
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continue
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if threads < block_m: # need at least 1 thread per row
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continue
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# Filter 3: occupancy >= 1 CTA/SM
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if cfg.occupancy_ctas(head_dim, elem_size) < 1:
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continue
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# Filter 4: PRE_LOAD_V register pressure check
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if pre_load_v:
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v_regs = block_n * head_dim * elem_size // 4 # fp16 → 2 per reg
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if v_regs > 128: # too many regs for V pre-load
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continue
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configs.append(cfg)
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return configs
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def rank_configs(configs: List[TritonConfig], head_dim: int = 256, elem_size: int = 2) -> List[TritonConfig]:
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"""Rank configs by estimated throughput, deduplicated.
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CCCL benchmark insight: for memory-bound kernels on BI-V100,
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the dominant factors are (in order):
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1. Total work per CTA (tile_elements) — amortizes launch overhead
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2. Occupancy × tile_size — total inflight bytes across SM
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3. Pipeline depth (num_stages) — matches bytes_in_flight window
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4. PRE_LOAD_V — reduces stalls when V is small enough for regs
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We penalize configs where threads < tile rows (wasted threads)
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and where SMEM utilization is very low (leaving bandwidth on table).
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"""
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# Deduplicate: (block_m, block_n, num_warps, num_stages, pre_load_v)
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seen = set()
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unique = []
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for cfg in configs:
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key = (cfg.block_m, cfg.block_n, cfg.num_warps, cfg.num_stages, cfg.pre_load_v)
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if key not in seen:
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seen.add(key)
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unique.append(cfg)
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def score(cfg: TritonConfig) -> float:
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tile = cfg.block_m * cfg.block_n
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occ = cfg.occupancy_ctas(head_dim, elem_size)
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smem = cfg.smem_bytes(head_dim, elem_size)
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smem_util = smem / HW["smem_per_block"]
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threads = cfg.num_warps * 32
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# Base: tile size × occupancy (bigger tiles, more parallelism)
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base = tile * max(occ, 1)
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# Bonus: stages=2 adds ~15% on BI-V100 (from CCCL babelstream data)
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stage_mult = 1.15 if cfg.num_stages == 2 else 1.0
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# Bonus: preload_v helps when reg pressure allows
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preload_mult = 1.05 if cfg.pre_load_v else 1.0
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# Penalty: threads >> block_m means wasted work per row
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thread_efficiency = min(1.0, cfg.block_m / threads)
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# Penalty: very low SMEM util means we could be doing more work
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smem_score = min(smem_util * 1.5, 1.0) # 67%+ util → score 1.0
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return base * stage_mult * preload_mult * thread_efficiency * smem_score
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return sorted(unique, key=score, reverse=True)
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def derive_partition_size() -> int:
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"""Derive optimal _PARTITION_SIZE for paged_attention.
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CCCL parallel: GridEvenShare partitioning.
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partition_size = tokens processed per CTA in V2.
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BI-V100: 16 SMs, each CTA handles one partition.
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For seq_len=4096, partition=512 → 8 partitions → 8 CTAs → only 8/16 SMs busy.
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partition=256 → 16 partitions → 16 CTAs → all SMs busy.
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But smaller partition → more inter-partition reduce overhead.
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Optimal: partition ≈ seq_len / (2 × sm_count) for long sequences
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For max_model_len=100K: 100000 / 32 ≈ 3125 → round to 2048 or 4096
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But V2 isn't used (forced V1), so this is academic for now.
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"""
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return 512 # Keep current — V2 is disabled
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def derive_prefill_config(head_dim: int = 256, elem_size: int = 2) -> Dict:
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"""Derive prefix_prefill.py BLOCK/BLOCK_N/NUM_WARPS.
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CCCL parallel: scan + reduce + transform (softmax + QKV matmul)
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SMEM model for prefix_prefill (context_attention_fwd_kernel):
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Q resident: BLOCK_M × head_dim × elem_size (stays across all K/V iters)
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K per iter: head_dim × BLOCK_N × elem_size (loaded, consumed, freed)
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softmax: BLOCK_M × 4 × 2 (m_i + l_i, fp32)
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Qwen3.6 head_dim=256, bf16:
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BLOCK_M=32, BLOCK_N=64: 8KB + 32KB + 256B = 40.25KB (82%) ✓
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BLOCK_M=64, BLOCK_N=64: 32KB + 32KB + 512B = 64.5KB (131%) ✗ OVERFLOW
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BLOCK_M=32, BLOCK_N=128: 8KB + 64KB + 256B = 72.25KB (147%) ✗ OVERFLOW
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BLOCK_M=64, BLOCK_N=32: 32KB + 16KB + 512B = 48.5KB (99%) TIGHT
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"""
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smem_limit = HW["smem_per_block"]
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# Try configs from largest to smallest
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candidates = [
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(64, 64, 4), # symmetric, ideal for NVIDIA
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(32, 64, 4), # asymmetric, better for SMEM-limited
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(64, 32, 4), # Q-heavy
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(32, 32, 4), # conservative
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(32, 32, 2), # minimal
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]
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for bm, bn, nw in candidates:
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q_smem = bm * head_dim * elem_size
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k_smem = head_dim * bn * elem_size
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softmax_smem = bm * 4 * 2
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total = q_smem + k_smem + softmax_smem
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if total <= smem_limit:
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return {
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"BLOCK_M": bm,
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"BLOCK_N": bn,
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"NUM_WARPS": nw,
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"num_stages": 1, # no async copy on BI-V100
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"smem_bytes": total,
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"smem_utilization": total / smem_limit,
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}
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# Fallback
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return {"BLOCK_M": 32, "BLOCK_N": 32, "NUM_WARPS": 4, "num_stages": 1,
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"smem_bytes": 32*256*2 + 256*32*2 + 32*8, "smem_utilization": 0.67}
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def main():
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print("=" * 70)
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print("muh gen_config: CCCL-derived Python-layer configs for BI-V100")
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print("=" * 70)
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# 1. Triton flash attention configs
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print("\n### 1. Triton flash attention autotune configs ###")
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print(f" head_dim={MODEL['head_dim']}, elem_size=2 (bf16)")
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all_configs = generate_triton_configs(MODEL["head_dim"], 2)
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ranked = rank_configs(all_configs, MODEL["head_dim"], 2)
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print(f" Generated {len(all_configs)} valid configs (from {16*4*3*2*2*3} combinations)")
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print(f" Top 10:")
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for i, cfg in enumerate(ranked[:10]):
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smem = cfg.smem_bytes(MODEL["head_dim"], 2)
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occ = cfg.occupancy_ctas(MODEL["head_dim"], 2)
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print(f" #{i+1}: M={cfg.block_m:3d} N={cfg.block_n:3d} "
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f"warps={cfg.num_warps} stages={cfg.num_stages} "
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f"preload_v={cfg.pre_load_v!s:5s} "
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f"smem={smem//1024}KB occ={occ} CTAs/SM")
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# 2. Prefix prefill config
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print("\n### 2. Prefix prefill config ###")
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prefill = derive_prefill_config(MODEL["head_dim"], 2)
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print(f" BLOCK_M={prefill['BLOCK_M']}, BLOCK_N={prefill['BLOCK_N']}, "
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f"NUM_WARPS={prefill['NUM_WARPS']}")
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print(f" SMEM={prefill['smem_bytes']}B ({prefill['smem_utilization']:.0%} of 48KB)")
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# 3. Partition size
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print("\n### 3. Paged attention config ###")
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ps = derive_partition_size()
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print(f" _PARTITION_SIZE={ps} (V2 disabled, V1 forced)")
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# 4. Summary of what's already applied vs what's new
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print("\n### 4. Applied vs pending ###")
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applied = [
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("_custom_ops.py SMEM=49152", "APPLIED"),
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("prefix_prefill.py BLOCK=64 BLOCK_N=64", "APPLIED"),
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("triton_flash_attention.py 8 BI-V100 configs", "APPLIED"),
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("computility-run.yaml max-model-len=100000", "APPLIED"),
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]
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pending = [
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(f"triton_flash_attention.py +{len(ranked[:20])-17} new configs", "PENDING"),
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("paged_attn.py V2 enable for long sequences", "PENDING (needs native V2)"),
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("prefix_prefill.py num_stages=2 experiment", "PENDING (needs cp.async support check)"),
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]
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for item, status in applied:
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print(f" ✓ {item}: {status}")
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for item, status in pending:
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print(f" ○ {item}: {status}")
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# 5. New configs to add to triton_flash_attention.py
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existing_signatures = set()
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# Current 17 configs from triton_flash_attention.py (manually extracted)
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existing_raw = [
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(256,64,8,1,False,2), (128,128,4,1,False,2), (256,128,8,1,False,2),
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(128,64,4,1,False,1), (128,64,4,1,True,3), (128,64,4,1,False,3),
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(64,64,8,1,False,4), (32,32,8,1,False,4), (16,16,4,1,False,1),
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# BI-V100 existing
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(64,32,4,1,False,2), (32,64,4,1,False,2), (64,64,4,1,False,2),
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(64,64,4,2,False,2), (32,64,4,2,True,2), (32,32,4,2,False,4),
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(32,32,4,2,True,4),
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]
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for m,n,w,s,p,we in existing_raw:
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existing_signatures.add((m,n,w,s,p))
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new_configs = []
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for cfg in ranked[:30]:
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sig = (cfg.block_m, cfg.block_n, cfg.num_warps, cfg.num_stages, cfg.pre_load_v)
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if sig not in existing_signatures:
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new_configs.append(cfg)
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existing_signatures.add(sig)
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print(f"\n### 5. New triton configs to add ({len(new_configs)}) ###")
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for cfg in new_configs[:15]:
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smem = cfg.smem_bytes(MODEL["head_dim"], 2)
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print(f" {cfg.to_triton_str()}")
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print(f" SMEM={smem//1024}KB, occupancy={cfg.occupancy_ctas(MODEL['head_dim'], 2)} CTAs/SM")
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if __name__ == "__main__":
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main()
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