[fix] reshape_paged_cache slot_mapping int64→int32 (C++ data_ptr<int>要求)
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@@ -149,9 +149,11 @@ def gelu_and_mul(input, output=None):
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# --- Cache (xllm_cache.so) ---
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# --- Cache (xllm_cache.so) ---
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# C++ reshape_paged_cache(slot_ids, keys, values, key_cache, value_cache)
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# C++ reshape_paged_cache(slot_ids, keys, values, key_cache, value_cache)
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# — slot_ids FIRST (not last!)
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# — slot_ids FIRST (not last!)
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# — slot_ids must be int32 (C++ uses data_ptr<int>), vllm passes int64
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def reshape_and_cache(key, value, key_cache, value_cache, slot_mapping):
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def reshape_and_cache(key, value, key_cache, value_cache, slot_mapping):
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"""Write KV to paged cache. C++ takes slot_ids as FIRST arg."""
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"""Write KV to paged cache. C++ takes slot_ids as FIRST arg, dtype=int32."""
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return _get("xllm_cache").reshape_paged_cache(slot_mapping, key, value,
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slot_mapping_i32 = slot_mapping.to(torch.int32)
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return _get("xllm_cache").reshape_paged_cache(slot_mapping_i32, key, value,
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key_cache, value_cache)
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key_cache, value_cache)
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# --- Attention (ix_moe_bridge.so) ---
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# --- Attention (ix_moe_bridge.so) ---
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@@ -149,9 +149,11 @@ def gelu_and_mul(input, output=None):
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# --- Cache (xllm_cache.so) ---
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# --- Cache (xllm_cache.so) ---
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# C++ reshape_paged_cache(slot_ids, keys, values, key_cache, value_cache)
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# C++ reshape_paged_cache(slot_ids, keys, values, key_cache, value_cache)
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# — slot_ids FIRST (not last!)
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# — slot_ids FIRST (not last!)
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# — slot_ids must be int32 (C++ uses data_ptr<int>), vllm passes int64
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def reshape_and_cache(key, value, key_cache, value_cache, slot_mapping):
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def reshape_and_cache(key, value, key_cache, value_cache, slot_mapping):
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"""Write KV to paged cache. C++ takes slot_ids as FIRST arg."""
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"""Write KV to paged cache. C++ takes slot_ids as FIRST arg, dtype=int32."""
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return _get("xllm_cache").reshape_paged_cache(slot_mapping, key, value,
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slot_mapping_i32 = slot_mapping.to(torch.int32)
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return _get("xllm_cache").reshape_paged_cache(slot_mapping_i32, key, value,
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key_cache, value_cache)
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key_cache, value_cache)
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# --- Attention (ix_moe_bridge.so) ---
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# --- Attention (ix_moe_bridge.so) ---
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