137 lines
4.6 KiB
Markdown
137 lines
4.6 KiB
Markdown
---
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license: cc-by-nc-4.0
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language:
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- en
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library_name: transformers
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tags:
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- verilog
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- rtl
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- hardware-design
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- eda
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- code-generation
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- chip-design
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base_model: Qwen/Qwen2.5-Coder-7B-Instruct
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pipeline_tag: text-generation
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model-index:
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- name: chipcraftx-rtlgen-7b
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results:
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- task:
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type: text-generation
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name: Verilog Code Generation
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dataset:
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name: VerilogEval-Human
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type: verilogeval
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metrics:
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- name: Functional Pass Rate (standalone)
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type: pass@1
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value: 36.5
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verified: true
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- name: Functional Pass Rate (ChipCraftX hybrid system)
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type: pass@1
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value: 98.7
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verified: true
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---
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# chipcraftx-rtlgen-7b
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**The local RTL generation engine powering [ChipCraftX](https://chipcraftx.io)** -- an AI platform that converts natural language specifications into synthesizable Verilog.
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`chipcraftx-rtlgen-7b` handles first-pass Verilog generation at zero API cost. Within the full ChipCraftX hybrid pipeline, the system achieves **98.7% functional pass rate on VerilogEval-Human (154/156)**.
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## Benchmark Results
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### VerilogEval-Human (156 problems, functional simulation)
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| Model | Parameters | Pass Rate |
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|-------|-----------|-----------|
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| VeriGen | 16B | 26.0% |
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| **chipcraftx-rtlgen-7b (standalone)** | **7B** | **36.5%** |
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| RTLCoder | 7B | 37.0% |
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| CodeV | 7B | 53.2% |
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| **ChipCraftX hybrid system** | **7B + Claude** | **98.7%** |
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## Model Details
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- **Base model**: [Qwen2.5-Coder-7B-Instruct](https://huggingface.co/Qwen/Qwen2.5-Coder-7B-Instruct)
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- **Fine-tuning**: QLoRA (rank 64, alpha 128) on 76,811 Verilog training samples
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- **Training**: 3 epochs, learning rate 2e-4, batch size 4
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- **Architecture**: 28 layers, 3584 hidden size, 28 attention heads
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- **Context window**: 4,096 tokens (generation), 32,768 (max position embeddings)
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- **Precision**: bfloat16
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## Usage
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### Transformers
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```python
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from transformers import AutoModelForCausalLM, AutoTokenizer
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model_name = "ChipCraftX/chipcraftx-rtlgen-7b"
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tokenizer = AutoTokenizer.from_pretrained(model_name)
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model = AutoModelForCausalLM.from_pretrained(model_name, torch_dtype="auto", device_map="auto")
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system_prompt = """You are ChipCraft-RTL, an expert Verilog design engineer.
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Generate synthesizable, lint-clean RTL that exactly matches the specification.
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Rules:
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- Output ONLY Verilog code (no prose, no markdown fences).
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- Use reg and wire types ONLY -- NEVER use logic.
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- Use always @(posedge clk) and always @(*) -- NEVER use always_ff or always_comb.
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- Module name MUST be TopModule."""
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spec = """Implement a module named TopModule with the following interface.
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- input clk
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- input reset
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- output [3:0] count
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The module should implement a 4-bit up counter with synchronous reset."""
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messages = [
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{"role": "system", "content": system_prompt},
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{"role": "user", "content": spec},
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]
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text = tokenizer.apply_chat_template(messages, tokenize=False, add_generation_prompt=True)
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inputs = tokenizer(text, return_tensors="pt").to(model.device)
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outputs = model.generate(**inputs, max_new_tokens=4096, temperature=0.2, do_sample=True)
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print(tokenizer.decode(outputs[0][inputs.input_ids.shape[1]:], skip_special_tokens=True))
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```
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### Ollama
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See [chipcraftx-rtlgen-7b-GGUF](https://huggingface.co/ChipCraftX/chipcraftx-rtlgen-7b-GGUF) for quantized GGUF versions compatible with Ollama and llama.cpp.
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## Training Data
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The model was fine-tuned on a proprietary dataset of 76,811 Verilog samples.
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## Intended Use
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This model is designed for:
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- First-pass RTL/Verilog code generation from natural language specs
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- Integration into automated EDA pipelines with validation feedback loops
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- Educational use in digital design courses
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- Rapid prototyping of hardware modules
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### Limitations
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- Standalone pass rate (36.5%) means ~2 out of 3 complex problems need iteration or human review
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- Strongest on combinational logic; weaker on FSMs and sequential designs
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- Outputs target Verilog-2001 / Icarus Verilog compatibility (not full SystemVerilog)
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- Should always be paired with EDA validation (iverilog, Yosys) before use in production
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## About ChipCraftX
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[ChipCraftX](https://chipcraftx.io) is an AI-powered platform that converts natural language specifications into verified, synthesizable hardware descriptions. The platform combines local and cloud models with automated EDA validation to achieve near-perfect scores on standard RTL benchmarks.
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## Citation
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```bibtex
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@misc{chipcraftx-rtlgen-7b,
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title={chipcraftx-rtlgen-7b: Local RTL Generation Engine for ChipCraftX},
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author={Eryilmaz, Cagri},
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year={2026},
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publisher={HuggingFace},
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url={https://huggingface.co/ChipCraftX/chipcraftx-rtlgen-7b}
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}
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```
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