Nellyw888/VeriReason-Qwen2.5-1.5b-RTLCoder-Verilog-GRPO-reasoning-tb
1
0
Fork 0
Code Issues Pull Requests Actions Projects Releases Wiki Activity
1 Commit 1 Branch 0 Tags
main
Commit Graph

1 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
ModelHub XC
bd30909b41 初始化项目，由ModelHub XC社区提供模型 
Model: Nellyw888/VeriReason-Qwen2.5-1.5b-RTLCoder-Verilog-GRPO-reasoning-tb
Source: Original Platform
 2026-08-02 08:21:20 +08:00