14c71b19e1
### What this PR does / why we need it?
This PR adds comprehensive documentation for the CPU binding feature on
Ascend NPUs. It includes:
- A detailed developer guide
(`docs/source/developer_guide/feature_guide/cpu_binding.md`) covering
the design, internal logic, allocation examples, and troubleshooting for
the CPU binding mechanism.
- A concise user guide
(`docs/source/user_guide/feature_guide/cpu_binding.md`) explaining the
core concepts, usage, and common issues for end-users.
- An update to `additional_config.md` to use consistent terminology for
binding strategies (`global-slicing` and `topo-affinity`).
This documentation is needed to help both developers and users
understand, use, and debug the CPU binding feature, which is critical
for performance on ARM+Ascend platforms.
### Does this PR introduce _any_ user-facing change?
No. This is a documentation-only update.
### How was this patch tested?
The documentation has been reviewed for clarity and technical accuracy.
The examples and descriptions align with the implementation in
`vllm_ascend/cpu_binding.py`.
- vLLM version: v0.16.0
- vLLM main:
4034c3d32e
---------
Signed-off-by: chenchuw886 <chenchuw@huawei.com>
Signed-off-by: c00818886 <chenchuwei@huawei.com>
Co-authored-by: chenchuw886 <chenchuw@huawei.com>
31 lines
464 B
Markdown
31 lines
464 B
Markdown
# Feature Guide
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This section provides a detailed usage guide of vLLM Ascend features.
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:::{toctree}
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:caption: Feature Guide
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:maxdepth: 1
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graph_mode
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cpu_binding
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quantization
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sleep_mode
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structured_output
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lora
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eplb_swift_balancer
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netloader
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Multi_Token_Prediction
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dynamic_batch
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kv_pool
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external_dp
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large_scale_ep
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ucm_deployment
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Fine_grained_TP
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layer_sharding
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speculative_decoding
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context_parallel
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npugraph_ex
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weight_prefetch
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sequence_parallelism
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batch_invariance
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:::
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