2 Commits

Author	SHA1	Message	Date
Agonixiaoxiao	7fc1a98489	add ut for kv tansfer module (#1531) ... ### What this PR does / why we need it? test kv data transfer contains connect,pipe,buffer ### Does this PR introduce _any_ user-facing change? N/A ### How was this patch tested? CI passed with new added test. --------- Signed-off-by: lixudong <lixudong@cmss.chinamobile.com> Signed-off-by: MengqingCao <cmq0113@163.com> Co-authored-by: lixudong <lixudong@cmss.chinamobile.com> Co-authored-by: MengqingCao <cmq0113@163.com>	2025-07-02 16:14:52 +08:00
wangyanhui-cmss	e5eea64b66	[CI/UT] Add ut for parallel_state.py (#1460) ... ### What this PR does / why we need it? Add ut for parallel_state.py ### Does this PR introduce _any_ user-facing change? N/A ### How was this patch tested? python -m unittest test_parallel_state.py --------- Signed-off-by: wangyanhui-cmss <wangyanhui_yewu@cmss.chinamobile.com>	2025-06-26 19:03:27 +08:00