[Bugfix] Qwen3Next support FlashComm1 (#6830)
### What this PR does / why we need it?
Support FlashComm1 for Qwen3-Next. Fix some padding problems in Sequence
Parallel (SP)
and resolve precision problems in shared_out when both FlashComm1 is
enabled.
### Does this PR introduce _any_ user-facing change?
No
### How was this patch tested?
CI
- vLLM version: v0.15.0
- vLLM main:
83b47f67b1
---------
Signed-off-by: zhaojiangjiang <zhaojiangjiang1@h-partners.com>
Co-authored-by: zhaojiangjiang <zhaojiangjiang1@h-partners.com>
This commit is contained in:
@@ -73,3 +73,38 @@ def test_qwen3_next_w8a8dynamic_distributed_tp4_ep():
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quantization="ascend",
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) as vllm_model:
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vllm_model.generate_greedy(example_prompts, max_tokens)
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@patch.dict(os.environ, {"VLLM_ASCEND_ENABLE_FLASHCOMM1": "1"})
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@patch.dict(os.environ, {"HCCL_BUFFSIZE": "1024"})
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def test_qwen3_next_distributed_mp_flash_comm_tp4():
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example_prompts = [
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"Hello, my name is",
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] * 4
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max_tokens = 5
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with VllmRunner("Qwen/Qwen3-Next-80B-A3B-Instruct",
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tensor_parallel_size=4,
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max_model_len=4096,
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gpu_memory_utilization=0.7,
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distributed_executor_backend="mp",
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enable_expert_parallel=True,
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enforce_eager=True) as vllm_model:
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vllm_model.generate_greedy(example_prompts, max_tokens)
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del vllm_model
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@patch.dict(os.environ, {"HCCL_BUFFSIZE": "1024"})
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def test_qwen3_next_distributed_mp_graph_mode_tp4():
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example_prompts = [
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"Hello, my name is",
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] * 4
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max_tokens = 5
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with VllmRunner("Qwen/Qwen3-Next-80B-A3B-Instruct",
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tensor_parallel_size=4,
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max_model_len=4096,
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gpu_memory_utilization=0.7,
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distributed_executor_backend="mp",
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enable_expert_parallel=True,
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enforce_eager=False) as vllm_model:
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vllm_model.generate_greedy(example_prompts, max_tokens)
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del vllm_model
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@@ -705,7 +705,11 @@ def _get_row_parallel_op(
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def get_parallel_op(disable_tp, prefix, layer, direct):
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if disable_tp or ("shared_experts" in prefix and shared_expert_dp_enabled()):
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if (
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disable_tp
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or ("shared_experts" in prefix and shared_expert_dp_enabled())
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or ("shared_expert" in prefix and shared_expert_dp_enabled())
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):
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return None, 0, 1
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custom_op: (
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MLPColumnParallelOp
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@@ -30,6 +30,7 @@ from vllm.v1.attention.backends.gdn_attn import GDNAttentionMetadata
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from vllm_ascend.ops.triton.fla.fused_qkvzba_split_reshape import fused_qkvzba_split_reshape_cat
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from vllm_ascend.ops.triton.fla.sigmoid_gating import fused_sigmoid_gating_delta_rule_update
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from vllm_ascend.ops.triton.fused_gdn_gating import fused_gdn_gating_patch
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from vllm_ascend.utils import enable_sp
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class AscendQwen3Next_GatedDeltaNet(nn.Module, MambaBase):
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@@ -44,13 +45,13 @@ class AscendQwen3Next_GatedDeltaNet(nn.Module, MambaBase):
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2. Core attention (custom op)
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3. Output projection
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"""
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num_tokens = hidden_states.size(0)
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# ============================================================
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# Part 1: Input Projection
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# ============================================================
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projected_states_qkvz, _ = self.in_proj_qkvz(hidden_states)
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projected_states_ba, _ = self.in_proj_ba(hidden_states)
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num_tokens = projected_states_qkvz.size(0)
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mixed_qkv, z, b, a = fused_qkvzba_split_reshape_cat(
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projected_states_qkvz,
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@@ -126,9 +127,10 @@ class AscendQwen3Next_GatedDeltaNet(nn.Module, MambaBase):
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num_actual_tokens = attn_metadata.num_actual_tokens
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num_accepted_tokens = attn_metadata.num_accepted_tokens
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mixed_qkv = mixed_qkv[:num_actual_tokens]
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b = b[:num_actual_tokens]
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a = a[:num_actual_tokens]
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if not enable_sp():
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mixed_qkv = mixed_qkv[:num_actual_tokens]
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b = b[:num_actual_tokens]
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a = a[:num_actual_tokens]
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# 1. Convolution sequence transformation
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conv_weights = self.conv1d.weight.view(self.conv1d.weight.size(0), self.conv1d.weight.size(2))
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@@ -292,11 +294,20 @@ class AscendQwen3Next_GatedDeltaNet(nn.Module, MambaBase):
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)
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merged_out.index_copy_(1, spec_token_indx, core_attn_out_spec)
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merged_out.index_copy_(1, non_spec_token_indx, core_attn_out_non_spec)
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core_attn_out[:num_actual_tokens] = merged_out.squeeze(0)
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if not enable_sp():
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core_attn_out[:num_actual_tokens] = merged_out.squeeze(0)
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else:
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core_attn_out[:num_actual_tokens] = merged_out.squeeze(0)[:num_actual_tokens]
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elif spec_sequence_masks is not None:
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core_attn_out[:num_actual_tokens] = core_attn_out_spec.squeeze(0)
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if not enable_sp():
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core_attn_out[:num_actual_tokens] = core_attn_out_spec.squeeze(0)
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else:
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core_attn_out[:num_actual_tokens] = core_attn_out_spec.squeeze(0)[:num_actual_tokens]
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else:
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core_attn_out[:num_actual_tokens] = core_attn_out_non_spec.squeeze(0)
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if not enable_sp():
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core_attn_out[:num_actual_tokens] = core_attn_out_non_spec.squeeze(0)
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else:
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core_attn_out[:num_actual_tokens] = core_attn_out_non_spec.squeeze(0)[:num_actual_tokens]
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Qwen3NextGatedDeltaNet.forward = AscendQwen3Next_GatedDeltaNet.forward
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@@ -1214,7 +1214,12 @@ class NPUModelRunner(GPUModelRunner):
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# Currently, Graph Mode and SP will both pad num_tokens,
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# Another possible condition is num_tokens_padded != num_tokens_unpadded
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# but this scope is way too big and the consequences are unpredictable
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old_num_reqs_padded = num_reqs_padded
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num_reqs_padded = self._pad_query_start_loc_for_fia(num_tokens_padded, num_reqs_padded, num_reqs)
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if enable_sp() and num_tokens_padded == num_tokens_unpadded:
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if num_reqs_padded > old_num_reqs_padded:
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num_reqs_padded = old_num_reqs_padded
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self.query_start_loc.np[num_reqs_padded + 1] = 0
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(attn_metadata, spec_decode_common_attn_metadata) = self._build_attention_metadata(
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num_tokens=num_tokens_unpadded
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