EngineX-Hygon/sglang
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64f296f8e6a67f4c58cb30730fcf7ee2a54b5b5b
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Author SHA1 Message Date
Lianmin Zheng
64f296f8e6 [Minor] Improve the style of server args (#10328) 2025-09-11 07:06:29 -07:00
Lianmin Zheng
956d805dde [Auto Sync] Update parallel_state.py (20250911) (#10326) 
Co-authored-by: github-actions[bot] <github-actions[bot]@users.noreply.github.com>
Co-authored-by: Byron Hsu <byronhsu1230@gmail.com>
 2025-09-11 06:36:29 -07:00
Yi Zhang
30c6e1f569 Qwen3-Next support (#10233) 
Co-authored-by: cao1zhg <114661107+cao1zhg@users.noreply.github.com>
Co-authored-by: ispobock <ispobaoke@gmail.com>
Co-authored-by: Binyao Jiang <byjiang1996@gmail.com>
Co-authored-by: hebiao064 <hebiaobuaa@gmail.com>
Co-authored-by: Lifu Huang <lifu.hlf@gmail.com>
Co-authored-by: qingquansong <ustcsqq@gmail.com>
Co-authored-by: Yaoyao Ding <dingyaoyao.cs@gmail.com>
Co-authored-by: Ke Bao <ISPObaoke@163.com>
Co-authored-by: Minglei Zhu <mingleizhu1122@gmail.com>
 2025-09-11 04:11:49 -07:00
Yineng Zhang
bfe01a5eef chore: upgrade v0.3.9.post2 sgl-kernel (#10297) 2025-09-11 04:10:29 -07:00
Hank Han
3dd6420a4d [CI] add pyproject.toml to deepseek w4a8 ci (#10314) 2025-09-11 02:10:50 -07:00
Yineng Zhang
532f998b0f chore: bump sgl-kernel 0.3.9.post2 (#10311) 2025-09-11 01:29:50 -07:00
Yineng Zhang
de15d1405a Revert "Fix flashinfer version in sgl-kernel (#10135)" (#10310) 2025-09-11 01:27:58 -07:00
Xiaoyu Zhang
37367da639 [fix CI] Fix logical condition in fused MoE layer for compressed tensor quantization (#10299) 2025-09-10 23:54:09 -07:00
Zaili Wang
ef959d7b85 [CPU] fix OOM when mem-fraction is not set (#9090) 2025-09-10 23:52:22 -07:00
BourneSun0527
4aa1e69bc7 [chore]Add sgl-router to npu images (#10229) 2025-09-10 23:51:16 -07:00
Yi Zhang
dc491b399d add flash linear attention triton kernel (#10239) 2025-09-10 21:47:20 -07:00
Even Zhou
5b64f006ec [Feature] Support DeepEP normal & Redundant Experts on NPU (#9881) 2025-09-10 20:35:26 -07:00
Yineng Zhang
5b7448de77 chore: bump sgl-kernel 0.3.9.post1 (#10294) 2025-09-10 18:26:34 -07:00
Yineng Zhang
6d55f60e77 Revert "[1/2] Optimizations and refactors about quant kernel (#9534)" (#10292) 2025-09-10 18:24:23 -07:00
Lianmin Zheng
033b75f559 [Auto Sync] Update serving_base.py, serving_chat.py, servin... (20250910) (#10282) 
Co-authored-by: github-actions[bot] <github-actions[bot]@users.noreply.github.com>
Co-authored-by: cctry <shiyang@x.ai>
 2025-09-10 16:58:59 -07:00
Xinyuan Tong
f3b5db6ee8 Feat: support disable tool parser (#10184) 2025-09-10 14:03:55 -07:00
Rain Jiang
2286e85e77 pass a_scale from fp8 quant result instead of hard code to 1.0f (#10241) 
Co-authored-by: Yichen Wang <yichen.wang@bytedance.com>
Co-authored-by: Jinwu Guo <641876696@qq.com>
 2025-09-10 12:56:05 -07:00
Hubert Lu
91b3555d2d Add tests to AMD CI for MI35x (#9662) 
Co-authored-by: Sai Enduri <saimanas.enduri@amd.com>
 2025-09-10 12:50:05 -07:00
Yi Zhang
9e2f7252db add dual stream for qwen2_moe (#10252) 2025-09-10 12:49:43 -07:00
Pavani Majety
21176b0093 [Bugfix] Fix Weightloading for the original nvidia/Deepseek-R1-FP4 checkpoint (#9940) 
Signed-off-by: Pavani Majety <pmajety@nvidia.com>
Co-authored-by: Yineng Zhang <me@zhyncs.com>
Co-authored-by: fzyzcjy <5236035+fzyzcjy@users.noreply.github.com>
 2025-09-10 12:00:23 -07:00
Lifu Huang
941002945b [1/2] Refactor LoRA to support backend-specific batch preprocessing. (#10251) 2025-09-10 09:58:37 -07:00
Keyang Ru
cda7e47ce7 [router] Add PD router mmlu test (#10256) 2025-09-10 08:47:24 -07:00
Lifu Huang
e903f695c8 Fix potential flakiness in test_lora_qwen3 (#10250) 2025-09-10 08:04:39 +00:00
Lianmin Zheng
27760fc1b6 [Auto Sync] Update io_struct.py (20250910) (#10262) 
Co-authored-by: github-actions[bot] <github-actions[bot]@users.noreply.github.com>
Co-authored-by: Kan Wu <wukanustc@gmail.com>
 2025-09-10 00:16:37 -07:00
Seunggeun Cho
0ac809de33 Fix assertion typo in tp_worker.py (#9954) 2025-09-10 13:43:50 +08:00
Lzhang-hub
4efe2c57c9 support vlm model spec bench (#10173) 2025-09-10 13:37:04 +08:00
huangtingwei
5be8c2f7f7 Page first direct IO kernel (#10060) 
Co-authored-by: Zhiqiang Xie <xiezhq@stanford.edu>
 2025-09-10 13:35:34 +08:00
Yiyu Liu
737d73ed5b Fix: the default choice is wrong for flashinfer mxfp4 moe precision (#10253) 2025-09-10 12:10:38 +08:00
Glen Liu
ebd0e1c18b [doc] add walkthrough for implementing and hosting a simple llama wrapper m… (#10093) 2025-09-10 12:05:06 +08:00
Sundara Raman Ramachandran
a1d038924b [Benchmark] Prefil-only benchmark scripts (#10240) 2025-09-10 10:59:07 +08:00
ryang
dccf52f9c8 [UT for RL] Add UT to cover release/resume memory case for moe model (#8803) 2025-09-09 19:25:12 -07:00
Lianmin Zheng
676a7b51bd make --speculative-draft-model an alias of --speculative-draft-model-path (#10246) 2025-09-09 19:12:24 -07:00
Kevin Tuan
15f993472c refactor(InternVL): Use gpu to preprocess the input image (#9795) 2025-09-09 19:09:04 -07:00
Lianmin Zheng
bcf1955f7e Revert "chore: upgrade v0.3.9 sgl-kernel" (#10245) 2025-09-09 19:05:20 -07:00
Lianmin Zheng
a06bf66425 [Auto Sync] Update collector.py, startup_func_log_and_timer... (20250910) (#10242) 
Co-authored-by: github-actions[bot] <github-actions[bot]@users.noreply.github.com>
Co-authored-by: cctry <shiyang@x.ai>
 2025-09-09 18:05:16 -07:00
Lianmin Zheng
bf72b80122 [Auto Sync] Update io_struct.py (20250909) (#10236) 
Co-authored-by: github-actions[bot] <github-actions[bot]@users.noreply.github.com>
Co-authored-by: cctry <shiyang@x.ai>
 2025-09-09 14:15:21 -07:00
Yi Zhang
8cbe1538ef Add mamba kernel (#10234) 2025-09-09 12:58:43 -07:00
Teng Ma
8471e5e616 [HiCache] feat: add mooncake backend extra config (#10213) 2025-09-09 12:50:00 -07:00
Lianmin Zheng
4582931ac3 Revert "Revert the changes on NCCL symmetric memory" (#10238) 2025-09-09 12:11:49 -07:00
Lianmin Zheng
d352c29aa0 Revert the changes on NCCL symmetric memory (#10210) 
Co-authored-by: Yineng Zhang <me@zhyncs.com>
 2025-09-09 11:01:33 -07:00
Yineng Zhang
d3ee70985f chore: upgrade v0.3.9 sgl-kernel (#10220) 2025-09-09 03:16:25 -07:00
Rain H
71fc7b7fad [Fix] KV-cache eviction mismatch across PP ranks in DeepSeek V3/R1 (#10214) 2025-09-09 02:07:13 -07:00
shaharmor98
9ab72f9895 add variable TP Decode > Prefill size support (#9960) 
Signed-off-by: Shahar Mor <smor@nvidia.com>
 2025-09-09 16:47:26 +08:00
Yineng Zhang
f3817cb0b2 chore: bump v0.3.9 sgl-kernel (#10208) 2025-09-09 01:40:05 -07:00
Lianmin Zheng
71133a0426 [Auto Sync] Update sampling_batch_info.py (20250909) (#10212) 
Co-authored-by: github-actions[bot] <github-actions[bot]@users.noreply.github.com>
Co-authored-by: cctry <shiyang@x.ai>
 2025-09-09 01:29:52 -07:00
Yiming
2cd94dd07e tool-call(dsv3): Fixed a parse problem when there are multiple function definitions in tool_calls (#10209) 2025-09-09 15:47:28 +08:00
Shangming Cai
f5f6b3b4b5 Refactor fused_add_rmsnorm import logic (#10207) 
Signed-off-by: Shangming Cai <csmthu@gmail.com>
 2025-09-09 00:23:58 -07:00
Yineng Zhang
94fb4e9e54 feat: support fa cute in sgl-kernel (#10205) 
Co-authored-by: cicirori <32845984+cicirori@users.noreply.github.com>
 2025-09-09 00:14:39 -07:00
blzheng
d1d4074c4e [CPU] Add gelu_and_mul kernel in sgl-kernel and add ut (#9300) 2025-09-08 23:23:13 -07:00
Keyang Ru
718f25ae6e Explicitly export CMAKE_BUILD_PARALLEL_LEVEL (#10193) 2025-09-08 22:35:27 -07:00