Yineng Zhang
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29daf498cd
|
fix cu118 link issue (#3421)
|
2025-02-09 18:16:44 +08:00 |
|
Shi Shuai
|
6702592d0e
|
[docs] Add multi-node inference example for SLURM in documentation (#3408)
Co-authored-by: zhaochenyang20 <zhaochen20@outlook.com>
Co-authored-by: aflah02 <aflah20082@iiitd.ac.in>
|
2025-02-08 21:45:14 -08:00 |
|
Yineng Zhang
|
60abdb3e7c
|
minor: cleanup test_eagle_infer (#3415)
|
2025-02-09 09:34:30 +08:00 |
|
Ying Sheng
|
7b4e61fff3
|
[Fix] Fix eagle with disable cuda graph (#3411)
|
2025-02-09 08:40:00 +08:00 |
|
Yineng Zhang
|
6222e1c228
|
add disable cuda graph unit test for eagle 2 (#3412)
|
2025-02-09 08:02:56 +08:00 |
|
Yineng Zhang
|
fad315cb8e
|
fix EAGLE 2 non greedy case (#3407)
Co-authored-by: Ying Sheng <sqy1415@gmail.com>
|
2025-02-09 07:28:34 +08:00 |
|
Yineng Zhang
|
f90db8bc07
|
fix typo
|
2025-02-08 22:16:42 +08:00 |
|
Ke Bao
|
d8ad597048
|
Add deepseek-v3 a100 serving example (#3404)
|
2025-02-08 22:13:52 +08:00 |
|
GaoYuYang
|
849f58d617
|
Update fused_moe's benchmark (#3346)
|
2025-02-08 21:58:21 +08:00 |
|
yiakwy-xpu-ml-framework-team
|
64480df495
|
[BUG] fix moe benchmark when bs*seq is small (#3382)
|
2025-02-08 15:39:44 +08:00 |
|
lukec
|
4530136e61
|
Add H20 fp8 w8a8 gemm config (#3386)
|
2025-02-08 15:36:31 +08:00 |
|
Zachary Streeter
|
0a6f18f068
|
added amd_configure.md to references (#3275)
Co-authored-by: HAI <hixiao@gmail.com>
Co-authored-by: Yineng Zhang <me@zhyncs.com>
Co-authored-by: zhaochenyang20 <zhaochen20@outlook.com>
|
2025-02-07 08:50:49 -08:00 |
|
Yineng Zhang
|
c1f5f99f60
|
chore: bump v0.4.2.post3 (#3369)
|
2025-02-07 08:20:03 -08:00 |
|
Yineng Zhang
|
fa82dfccdd
|
fix EagleVerifyInput (#3378)
|
2025-02-07 22:30:43 +08:00 |
|
Yineng Zhang
|
5da3d21c8b
|
update pr-test ci (#3376)
|
2025-02-07 21:08:35 +08:00 |
|
Yineng Zhang
|
f287037673
|
update sgl-kernel version (#3374)
|
2025-02-07 20:51:06 +08:00 |
|
Yineng Zhang
|
f9905d59a8
|
support speculative decoding kernel in sgl-kernel (#3373)
Co-authored-by: Ying Sheng <sqy1415@gmail.com>
|
2025-02-07 20:29:51 +08:00 |
|
Yineng Zhang
|
45c87e083f
|
fix undefined symbol cudaGetDriverEntryPointByVersion (#3372)
|
2025-02-07 19:32:45 +08:00 |
|
Yineng Zhang
|
2b1808cec4
|
update unit test in AMD CI (#3366)
|
2025-02-07 17:25:16 +08:00 |
|
lizamd
|
e868d0b60e
|
update waves_per_eu to 1 (#3356)
|
2025-02-07 13:08:06 +08:00 |
|
Shi Shuai
|
591e751e07
|
Fix: Runtime error for function calling (#3300)
|
2025-02-06 20:52:01 -08:00 |
|
Chayenne
|
40022d075a
|
Feature: Fix the binding error in Llama (#3355)
|
2025-02-06 20:19:24 -08:00 |
|
Liangjun Song
|
823148e7f0
|
Docs: Add deepseek usage and add multi-node, credit to lycanlancelot (#3314)
Co-authored-by: Shi Shuai <126407087+shuaills@users.noreply.github.com>
Co-authored-by: Chayenne <zhaochen20@outlook.com>
Co-authored-by: Yineng Zhang <me@zhyncs.com>
|
2025-02-06 19:45:00 -08:00 |
|
Chayenne
|
76ca91dff2
|
Docs/CI: Enable Fake Finish for Docs Only PR (#3350)
|
2025-02-06 19:33:31 -08:00 |
|
Xiaoyu Zhang
|
cdae77b03d
|
optimize moe_align_kernel cuda (#3347)
|
2025-02-07 00:53:46 +08:00 |
|
Yineng Zhang
|
adeee15204
|
fix sgl-kernel build failure on AMD (#3352)
|
2025-02-07 00:35:59 +08:00 |
|
Ke Bao
|
6792411e7f
|
[Doc] Add optimization option guide for deepseek v3 (#3349)
|
2025-02-06 23:28:09 +08:00 |
|
Yineng Zhang
|
7348d9627e
|
add AMD guide for DeepSeek-R1 (#3338)
|
2025-02-06 16:54:40 +08:00 |
|
Yineng Zhang
|
25ed22b685
|
update pull request template (#3337)
|
2025-02-06 16:48:02 +08:00 |
|
saienduri
|
200d3b1608
|
Add sgl-kernel to MI300 CI paths tested. (#3335)
Co-authored-by: HAI <hixiao@gmail.com>
|
2025-02-06 00:45:38 -08:00 |
|
Xiaoyu Zhang
|
ad3499858e
|
clean moe align block kernel code and add acc test (#3332)
|
2025-02-06 16:42:36 +08:00 |
|
Wen-Heng (Jack) Chung
|
32de54ed1a
|
[ROCm] Fix fp8 unrolledx4 matmul kernel. (#3325)
Co-authored-by: HAI <hixiao@gmail.com>
|
2025-02-05 18:44:15 -08:00 |
|
saienduri
|
2d9c319594
|
Docker switch (#3327)
Co-authored-by: HAI <hixiao@gmail.com>
|
2025-02-05 18:06:50 -08:00 |
|
Yineng Zhang
|
07e58a2dcb
|
update README (#3324)
|
2025-02-06 07:13:05 +08:00 |
|
saienduri
|
04d8cd2088
|
Initial Enablement of CI on MI300 (#3168)
|
2025-02-05 10:45:12 -08:00 |
|
Ke Bao
|
a322051e31
|
Support custom mask for Triton attention (#3317)
|
2025-02-06 01:16:02 +08:00 |
|
Ke Bao
|
de5533341e
|
Update Triton extend backend interface (#3309)
|
2025-02-05 18:12:22 +08:00 |
|
Yineng Zhang
|
7aad8d1854
|
chore: bump v0.4.2.post2 (#3313)
|
2025-02-05 17:35:02 +08:00 |
|
Baizhou Zhang
|
76fa2d152c
|
Fix lora flashinfer import bug on ROCM (#3312)
|
2025-02-05 16:36:49 +08:00 |
|
Wen-Heng (Jack) Chung
|
7ab84948d8
|
[ROCm] Logic to decide whether to used manually unrolled kernel. (#3306)
|
2025-02-04 19:12:20 -08:00 |
|
kk
|
4885b90802
|
Use forward_cuda to execute custom op for hip platform (#3305)
Co-authored-by: wunhuang <wunhuang@amd.com>
|
2025-02-05 02:58:17 +00:00 |
|
Wen-Heng (Jack) Chung
|
c2723a42a5
|
[ROCm] Manually unroll _w8a8_block_fp8_matmul kernel on AMD GPU. (#3299)
|
2025-02-05 07:15:40 +08:00 |
|
Wen-Heng (Jack) Chung
|
c7256ca836
|
[ROCm] Add tuning configs for AMD Radeon Graphics. (#3294)
|
2025-02-04 10:34:57 -08:00 |
|
Yineng Zhang
|
6186a8f889
|
update flashinfer install index url (#3293)
|
2025-02-05 00:44:35 +08:00 |
|
Ke Bao
|
a07364ccc5
|
Update Triton decode backend interface (#3292)
|
2025-02-04 23:26:04 +08:00 |
|
HAI
|
2c1a695ff1
|
ROCm: sgl-kernel enablement starting with sgl_moe_align_block (#3287)
|
2025-02-04 21:44:44 +08:00 |
|
Yineng Zhang
|
d39899e85c
|
upgrade flashinfer v0.2.0.post2 (#3288)
Co-authored-by: pankajroark <pankajroark@users.noreply.github.com>
|
2025-02-04 21:41:40 +08:00 |
|
Baizhou Zhang
|
70817a7eae
|
[Feature] Define backends and add Triton backend for Lora (#3161)
Co-authored-by: Ying Sheng <sqy1415@gmail.com>
|
2025-02-03 22:09:13 -08:00 |
|
simveit
|
7b5a374114
|
Update server args doc (#3273)
Co-authored-by: Shi Shuai <126407087+shuaills@users.noreply.github.com>
|
2025-02-03 23:39:41 +00:00 |
|
Yineng Zhang
|
4b6f62e2bc
|
add Atlas Cloud for Adoption and Sponsorship (#3276)
|
2025-02-04 05:31:30 +08:00 |
|