commit 465c9315bdad46301e221f7a7cde870e489e8529 Author: ModelHub XC Date: Sat May 9 17:18:23 2026 +0800 初始化项目，由ModelHub XC社区提供模型 Model: mradermacher/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF Source: Original Platform diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..591baed --- /dev/null +++ b/.gitattributes @@ -0,0 +1,47 @@ +*.7z filter=lfs diff=lfs merge=lfs -text +*.arrow filter=lfs diff=lfs merge=lfs -text +*.bin filter=lfs diff=lfs merge=lfs -text +*.bz2 filter=lfs diff=lfs merge=lfs -text +*.ckpt filter=lfs diff=lfs merge=lfs -text +*.ftz filter=lfs diff=lfs merge=lfs -text +*.gz filter=lfs diff=lfs merge=lfs -text +*.h5 filter=lfs diff=lfs merge=lfs -text +*.joblib filter=lfs diff=lfs merge=lfs -text +*.lfs.* filter=lfs diff=lfs merge=lfs -text +*.mlmodel filter=lfs diff=lfs merge=lfs -text +*.model filter=lfs diff=lfs merge=lfs -text +*.msgpack filter=lfs diff=lfs merge=lfs -text +*.npy filter=lfs diff=lfs merge=lfs -text +*.npz filter=lfs diff=lfs merge=lfs -text +*.onnx filter=lfs diff=lfs merge=lfs -text +*.ot filter=lfs diff=lfs merge=lfs -text +*.parquet filter=lfs diff=lfs merge=lfs -text +*.pb filter=lfs diff=lfs merge=lfs -text +*.pickle filter=lfs diff=lfs merge=lfs -text +*.pkl filter=lfs diff=lfs merge=lfs -text +*.pt filter=lfs diff=lfs merge=lfs -text +*.pth filter=lfs diff=lfs merge=lfs -text +*.rar filter=lfs diff=lfs merge=lfs -text +*.safetensors filter=lfs diff=lfs merge=lfs -text +saved_model/**/* filter=lfs diff=lfs merge=lfs -text +*.tar.* filter=lfs diff=lfs merge=lfs -text +*.tar filter=lfs diff=lfs merge=lfs -text +*.tflite filter=lfs diff=lfs merge=lfs -text +*.tgz filter=lfs diff=lfs merge=lfs -text +*.wasm filter=lfs diff=lfs merge=lfs -text +*.xz filter=lfs diff=lfs merge=lfs -text +*.zip filter=lfs diff=lfs merge=lfs -text +*.zst filter=lfs diff=lfs merge=lfs -text +*tfevents* filter=lfs diff=lfs merge=lfs -text +VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.f16.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q4_K_S.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q2_K.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q8_0.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q6_K.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_M.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_S.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_L.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q4_K_M.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q5_K_S.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q5_K_M.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.IQ4_XS.gguf filter=lfs diff=lfs merge=lfs -text diff --git a/README.md b/README.md new file mode 100644 index 0000000..104c9f4 --- /dev/null +++ b/README.md @@ -0,0 +1,76 @@ +--- +base_model: Nellyw888/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb +language: +- en +library_name: transformers +mradermacher: + readme_rev: 1 +quantized_by: mradermacher +tags: +- verilog +- reasoning +- reinforcement-learning +- rtl +--- +## About + + + + + + + + + +static quants of https://huggingface.co/Nellyw888/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb + + + +***For a convenient overview and download list, visit our [model page for this model](https://hf.tst.eu/model#VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF).*** + +weighted/imatrix quants seem not to be available (by me) at this time. If they do not show up a week or so after the static ones, I have probably not planned for them. Feel free to request them by opening a Community Discussion. +## Usage + +If you are unsure how to use GGUF files, refer to one of [TheBloke's +READMEs](https://huggingface.co/TheBloke/KafkaLM-70B-German-V0.1-GGUF) for +more details, including on how to concatenate multi-part files. + +## Provided Quants + +(sorted by size, not necessarily quality. IQ-quants are often preferable over similar sized non-IQ quants) + +| Link | Type | Size/GB | Notes | +|:-----|:-----|--------:|:------| +| [GGUF](https://huggingface.co/mradermacher/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q2_K.gguf) | Q2_K | 2.6 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_S.gguf) | Q3_K_S | 3.0 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_M.gguf) | Q3_K_M | 3.4 | lower quality | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_L.gguf) | Q3_K_L | 3.7 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.IQ4_XS.gguf) | IQ4_XS | 3.7 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q4_K_S.gguf) | Q4_K_S | 4.0 | fast, recommended | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q4_K_M.gguf) | Q4_K_M | 4.2 | fast, recommended | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q5_K_S.gguf) | Q5_K_S | 4.8 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q5_K_M.gguf) | Q5_K_M | 4.9 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q6_K.gguf) | Q6_K | 5.6 | very good quality | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q8_0.gguf) | Q8_0 | 7.3 | fast, best quality | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.f16.gguf) | f16 | 13.6 | 16 bpw, overkill | + +Here is a handy graph by ikawrakow comparing some lower-quality quant +types (lower is better): + +![image.png](https://www.nethype.de/huggingface_embed/quantpplgraph.png) + +And here are Artefact2's thoughts on the matter: +https://gist.github.com/Artefact2/b5f810600771265fc1e39442288e8ec9 + +## FAQ / Model Request + +See https://huggingface.co/mradermacher/model_requests for some answers to +questions you might have and/or if you want some other model quantized. + +## Thanks + +I thank my company, [nethype GmbH](https://www.nethype.de/), for letting +me use its servers and providing upgrades to my workstation to enable +this work in my free time. + + diff --git a/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.IQ4_XS.gguf b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.IQ4_XS.gguf new file mode 100644 index 0000000..25754cf --- /dev/null +++ b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.IQ4_XS.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:f5728a9831ac86c226e44a9d0799360e184fcd8768b76e4993529b22c24bbd73 +size 3647607488 diff --git a/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q2_K.gguf b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q2_K.gguf new file mode 100644 index 0000000..de83473 --- /dev/null +++ b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q2_K.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7ed0a94b9c94c8087714566b79af561a43c17f5b31561293f8136ff10ac465b3 +size 2532941504 diff --git a/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_L.gguf b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_L.gguf new file mode 100644 index 0000000..181ab6f --- /dev/null +++ b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_L.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c66f9f7c0a4292c4a9f0cda900a156b4d5642989bb64058f917876a200840879 +size 3597195456 diff --git a/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_M.gguf b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_M.gguf new file mode 100644 index 0000000..cda91b6 --- /dev/null +++ b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_M.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:34983a94bf6cf7f827169274c6e8046a23ac9910cd416021443ce39292a62e35 +size 3298089152 diff --git a/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_S.gguf b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_S.gguf new file mode 100644 index 0000000..5419992 --- /dev/null +++ b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_S.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:494324392b02d80c531b4c62c62cc680f48729ebee6d29f24f657275e4cd96cc +size 2948389056 diff --git a/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q4_K_M.gguf b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q4_K_M.gguf new file mode 100644 index 0000000..35a1359 --- /dev/null +++ b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q4_K_M.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c623971e30ea85861bfa340d240d71f2df45e679658aa4c9ff95f549351e8ff1 +size 4081097408 diff --git a/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q4_K_S.gguf b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q4_K_S.gguf new file mode 100644 index 0000000..e52165e --- /dev/null +++ b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q4_K_S.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:bc09aa7285b080beaad9be48a286de2af1b14018bc927f8a1b66d4d80e34a279 +size 3856833216 diff --git a/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q5_K_M.gguf b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q5_K_M.gguf new file mode 100644 index 0000000..6139669 --- /dev/null +++ b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q5_K_M.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7890fddc337417ed43578f33c8f1ec7c6eb0187983150fa6228ba1ddde3c4e00 +size 4783258304 diff --git a/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q5_K_S.gguf b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q5_K_S.gguf new file mode 100644 index 0000000..38c293c --- /dev/null +++ b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q5_K_S.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:f061922bd1feddb295904f83237c8f86682e1ee327b7400e120f64b001528fad +size 4651793088 diff --git a/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q6_K.gguf b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q6_K.gguf new file mode 100644 index 0000000..72892c8 --- /dev/null +++ b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q6_K.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:d74631219cba22e34af8b03d93f9f0987d39b6d8b0df6b6d563c8ecc046b216e +size 5529304256 diff --git a/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q8_0.gguf b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q8_0.gguf new file mode 100644 index 0000000..83f504a --- /dev/null +++ b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.Q8_0.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:fa3ed0c1c96edd5a6c098f930128783aef2e257320e050317f7ea0f1dd30c072 +size 7161231552 diff --git a/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.f16.gguf b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.f16.gguf new file mode 100644 index 0000000..4386b94 --- /dev/null +++ b/VeriReason-codeLlama-7b-RTLCoder-Verilog-GRPO-reasoning-tb.f16.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:4b71eba9d076874bfa09aa3e6c3802d11d0fcc26ccd701c30022218e638b08f6 +size 13478369472