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VeriReason-Qwen2.5-7b-RTLCo…/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q5_K_M.gguf
ModelHub XC f162fc6eca 初始化项目,由ModelHub XC社区提供模型
Model: mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF
Source: Original Platform
2026-06-04 02:56:16 +08:00

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version https://git-lfs.github.com/spec/v1
oid sha256:1e208129c9a3055cb937eac1c4920f170c2236729e7d75a4cd326b50d894d409
size 5444832672