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VeriReason-Qwen2.5-7b-RTLCo…/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ2_M.gguf
ModelHub XC f162fc6eca 初始化项目,由ModelHub XC社区提供模型
Model: mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF
Source: Original Platform
2026-06-04 02:56:16 +08:00

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version https://git-lfs.github.com/spec/v1
oid sha256:e0d32bd312ed4883b5fd385e6cbd657b13464977ac5e9a41d0dea22b8718be7f
size 2780343712