mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF
1
0
Fork 0
Code Issues Pull Requests Actions Projects Releases Wiki Activity
1 Commit 1 Branch 0 Tags
main
Commit Graph

1 Commits

Author SHA1 Message Date
ModelHub XC
f162fc6eca 初始化项目，由ModelHub XC社区提供模型 
Model: mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF
Source: Original Platform
 2026-06-04 02:56:16 +08:00