From f162fc6eca6342d517f8c05c1570de643175d506 Mon Sep 17 00:00:00 2001 From: ModelHub XC Date: Thu, 4 Jun 2026 02:56:16 +0800 Subject: [PATCH] =?UTF-8?q?=E5=88=9D=E5=A7=8B=E5=8C=96=E9=A1=B9=E7=9B=AE?= =?UTF-8?q?=EF=BC=8C=E7=94=B1ModelHub=20XC=E7=A4=BE=E5=8C=BA=E6=8F=90?= =?UTF-8?q?=E4=BE=9B=E6=A8=A1=E5=9E=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Model: mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF Source: Original Platform --- .gitattributes | 60 +++++++++++++ README.md | 87 +++++++++++++++++++ ...er-Verilog-GRPO-reasoning-tb.i1-IQ1_M.gguf | 3 + ...er-Verilog-GRPO-reasoning-tb.i1-IQ1_S.gguf | 3 + ...er-Verilog-GRPO-reasoning-tb.i1-IQ2_M.gguf | 3 + ...er-Verilog-GRPO-reasoning-tb.i1-IQ2_S.gguf | 3 + ...r-Verilog-GRPO-reasoning-tb.i1-IQ2_XS.gguf | 3 + ...-Verilog-GRPO-reasoning-tb.i1-IQ2_XXS.gguf | 3 + ...er-Verilog-GRPO-reasoning-tb.i1-IQ3_M.gguf | 3 + ...er-Verilog-GRPO-reasoning-tb.i1-IQ3_S.gguf | 3 + ...r-Verilog-GRPO-reasoning-tb.i1-IQ3_XS.gguf | 3 + ...-Verilog-GRPO-reasoning-tb.i1-IQ3_XXS.gguf | 3 + ...r-Verilog-GRPO-reasoning-tb.i1-IQ4_NL.gguf | 3 + ...r-Verilog-GRPO-reasoning-tb.i1-IQ4_XS.gguf | 3 + ...der-Verilog-GRPO-reasoning-tb.i1-Q2_K.gguf | 3 + ...r-Verilog-GRPO-reasoning-tb.i1-Q2_K_S.gguf | 3 + ...r-Verilog-GRPO-reasoning-tb.i1-Q3_K_L.gguf | 3 + ...r-Verilog-GRPO-reasoning-tb.i1-Q3_K_M.gguf | 3 + ...r-Verilog-GRPO-reasoning-tb.i1-Q3_K_S.gguf | 3 + ...der-Verilog-GRPO-reasoning-tb.i1-Q4_0.gguf | 3 + ...der-Verilog-GRPO-reasoning-tb.i1-Q4_1.gguf | 3 + ...r-Verilog-GRPO-reasoning-tb.i1-Q4_K_M.gguf | 3 + ...r-Verilog-GRPO-reasoning-tb.i1-Q4_K_S.gguf | 3 + ...r-Verilog-GRPO-reasoning-tb.i1-Q5_K_M.gguf | 3 + ...r-Verilog-GRPO-reasoning-tb.i1-Q5_K_S.gguf | 3 + ...der-Verilog-GRPO-reasoning-tb.i1-Q6_K.gguf | 3 + imatrix.dat | 3 + 27 files changed, 222 insertions(+) create mode 100644 .gitattributes create mode 100644 README.md create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ1_M.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ1_S.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ2_M.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ2_S.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ2_XS.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ2_XXS.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ3_M.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ3_S.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ3_XS.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ3_XXS.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ4_NL.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ4_XS.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q2_K.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q2_K_S.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q3_K_L.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q3_K_M.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q3_K_S.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q4_0.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q4_1.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q4_K_M.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q4_K_S.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q5_K_M.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q5_K_S.gguf create mode 100644 VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q6_K.gguf create mode 100644 imatrix.dat diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..4356644 --- /dev/null +++ b/.gitattributes @@ -0,0 +1,60 @@ +*.7z filter=lfs diff=lfs merge=lfs -text +*.arrow filter=lfs diff=lfs merge=lfs -text +*.bin filter=lfs diff=lfs merge=lfs -text +*.bz2 filter=lfs diff=lfs merge=lfs -text +*.ckpt filter=lfs diff=lfs merge=lfs -text +*.ftz filter=lfs diff=lfs merge=lfs -text +*.gz filter=lfs diff=lfs merge=lfs -text +*.h5 filter=lfs diff=lfs merge=lfs -text +*.joblib filter=lfs diff=lfs merge=lfs -text +*.lfs.* filter=lfs diff=lfs merge=lfs -text +*.mlmodel filter=lfs diff=lfs merge=lfs -text +*.model filter=lfs diff=lfs merge=lfs -text +*.msgpack filter=lfs diff=lfs merge=lfs -text +*.npy filter=lfs diff=lfs merge=lfs -text +*.npz filter=lfs diff=lfs merge=lfs -text +*.onnx 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+VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ1_S.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q5_K_M.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q4_0.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ3_XS.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q4_1.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ3_S.gguf filter=lfs diff=lfs merge=lfs -text diff --git a/README.md b/README.md new file mode 100644 index 0000000..eaaabab --- /dev/null +++ b/README.md @@ -0,0 +1,87 @@ +--- +base_model: Nellyw888/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb +datasets: +- Nellyw888/VeriReason-RTL-Coder_7b_reasoning_tb +language: +- en +library_name: transformers +mradermacher: + readme_rev: 1 +quantized_by: mradermacher +tags: +- verilog +- reasoning +- reinforcement-learning +- rtl +--- +## About + + + + + + +weighted/imatrix quants of https://huggingface.co/Nellyw888/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb + + + +***For a convenient overview and download list, visit our [model page for this model](https://hf.tst.eu/model#VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF).*** + +static quants are available at https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF +## Usage + +If you are unsure how to use GGUF files, refer to one of [TheBloke's +READMEs](https://huggingface.co/TheBloke/KafkaLM-70B-German-V0.1-GGUF) for +more details, including on how to concatenate multi-part files. + +## Provided Quants + +(sorted by size, not necessarily quality. IQ-quants are often preferable over similar sized non-IQ quants) + +| Link | Type | Size/GB | Notes | +|:-----|:-----|--------:|:------| +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ1_S.gguf) | i1-IQ1_S | 2.0 | for the desperate | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ1_M.gguf) | i1-IQ1_M | 2.1 | mostly desperate | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ2_XXS.gguf) | i1-IQ2_XXS | 2.4 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ2_XS.gguf) | i1-IQ2_XS | 2.6 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ2_S.gguf) | i1-IQ2_S | 2.7 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ2_M.gguf) | i1-IQ2_M | 2.9 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q2_K_S.gguf) | i1-Q2_K_S | 2.9 | very low quality | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q2_K.gguf) | i1-Q2_K | 3.1 | IQ3_XXS probably better | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ3_XXS.gguf) | i1-IQ3_XXS | 3.2 | lower quality | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ3_XS.gguf) | i1-IQ3_XS | 3.4 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q3_K_S.gguf) | i1-Q3_K_S | 3.6 | IQ3_XS probably better | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ3_S.gguf) | i1-IQ3_S | 3.6 | beats Q3_K* | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ3_M.gguf) | i1-IQ3_M | 3.7 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q3_K_M.gguf) | i1-Q3_K_M | 3.9 | IQ3_S probably better | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q3_K_L.gguf) | i1-Q3_K_L | 4.2 | IQ3_M probably better | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ4_XS.gguf) | i1-IQ4_XS | 4.3 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ4_NL.gguf) | i1-IQ4_NL | 4.5 | prefer IQ4_XS | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q4_0.gguf) | i1-Q4_0 | 4.5 | fast, low quality | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q4_K_S.gguf) | i1-Q4_K_S | 4.6 | optimal size/speed/quality | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q4_K_M.gguf) | i1-Q4_K_M | 4.8 | fast, recommended | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q4_1.gguf) | i1-Q4_1 | 5.0 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q5_K_S.gguf) | i1-Q5_K_S | 5.4 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q5_K_M.gguf) | i1-Q5_K_M | 5.5 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb-i1-GGUF/resolve/main/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-Q6_K.gguf) | i1-Q6_K | 6.4 | practically like static Q6_K | + +Here is a handy graph by ikawrakow comparing some lower-quality quant +types (lower is better): + +![image.png](https://www.nethype.de/huggingface_embed/quantpplgraph.png) + +And here are Artefact2's thoughts on the matter: +https://gist.github.com/Artefact2/b5f810600771265fc1e39442288e8ec9 + +## FAQ / Model Request + +See https://huggingface.co/mradermacher/model_requests for some answers to +questions you might have and/or if you want some other model quantized. + +## Thanks + +I thank my company, [nethype GmbH](https://www.nethype.de/), for letting +me use its servers and providing upgrades to my workstation to enable +this work in my free time. Additional thanks to [@nicoboss](https://huggingface.co/nicoboss) for giving me access to his private supercomputer, enabling me to provide many more imatrix quants, at much higher quality, than I would otherwise be able to. + + diff --git a/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ1_M.gguf b/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ1_M.gguf new file mode 100644 index 0000000..0d90199 --- /dev/null +++ b/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ1_M.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:2cd63d1bede1d70744d624c400fc29a8634221f91cf8e4baf1368a5d75e6b457 +size 2042197408 diff --git a/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ1_S.gguf b/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ1_S.gguf new file mode 100644 index 0000000..f91b975 --- /dev/null +++ b/VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb.i1-IQ1_S.gguf @@ -0,0 +1,3 @@ +version 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