Files
VeriReason-Qwen2.5-3b-RTLCo…/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.IQ4_XS.gguf
ModelHub XC 63527ab1ab 初始化项目,由ModelHub XC社区提供模型
Model: mradermacher/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF
Source: Original Platform
2026-05-09 00:17:13 +08:00

4 lines
135 B
Plaintext

version https://git-lfs.github.com/spec/v1
oid sha256:65251c5fdfe1be9bc10cc73d475b7bbf775b5e43721310496224aa989c962746
size 1753183552