From 63527ab1ab4f772b86114fc6e542961f384bdc4d Mon Sep 17 00:00:00 2001 From: ModelHub XC Date: Sat, 9 May 2026 00:17:13 +0800 Subject: [PATCH] =?UTF-8?q?=E5=88=9D=E5=A7=8B=E5=8C=96=E9=A1=B9=E7=9B=AE?= =?UTF-8?q?=EF=BC=8C=E7=94=B1ModelHub=20XC=E7=A4=BE=E5=8C=BA=E6=8F=90?= =?UTF-8?q?=E4=BE=9B=E6=A8=A1=E5=9E=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Model: mradermacher/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF Source: Original Platform --- .gitattributes | 47 ++++++++++++ README.md | 76 +++++++++++++++++++ ...oder-Verilog-GRPO-reasoning-tb.IQ4_XS.gguf | 3 + ...LCoder-Verilog-GRPO-reasoning-tb.Q2_K.gguf | 3 + ...oder-Verilog-GRPO-reasoning-tb.Q3_K_L.gguf | 3 + ...oder-Verilog-GRPO-reasoning-tb.Q3_K_M.gguf | 3 + ...oder-Verilog-GRPO-reasoning-tb.Q3_K_S.gguf | 3 + ...oder-Verilog-GRPO-reasoning-tb.Q4_K_M.gguf | 3 + ...oder-Verilog-GRPO-reasoning-tb.Q4_K_S.gguf | 3 + ...oder-Verilog-GRPO-reasoning-tb.Q5_K_M.gguf | 3 + ...oder-Verilog-GRPO-reasoning-tb.Q5_K_S.gguf | 3 + ...LCoder-Verilog-GRPO-reasoning-tb.Q6_K.gguf | 3 + ...LCoder-Verilog-GRPO-reasoning-tb.Q8_0.gguf | 3 + ...TLCoder-Verilog-GRPO-reasoning-tb.f16.gguf | 3 + 14 files changed, 159 insertions(+) create mode 100644 .gitattributes create mode 100644 README.md create mode 100644 VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.IQ4_XS.gguf create mode 100644 VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q2_K.gguf create mode 100644 VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_L.gguf create mode 100644 VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_M.gguf create mode 100644 VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_S.gguf create mode 100644 VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q4_K_M.gguf create mode 100644 VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q4_K_S.gguf create mode 100644 VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q5_K_M.gguf create mode 100644 VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q5_K_S.gguf create mode 100644 VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q6_K.gguf create mode 100644 VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q8_0.gguf create mode 100644 VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.f16.gguf diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..e99e655 --- /dev/null +++ b/.gitattributes @@ -0,0 +1,47 @@ +*.7z filter=lfs diff=lfs merge=lfs -text +*.arrow filter=lfs diff=lfs merge=lfs -text +*.bin filter=lfs diff=lfs merge=lfs -text +*.bz2 filter=lfs diff=lfs merge=lfs -text +*.ckpt filter=lfs diff=lfs merge=lfs -text +*.ftz filter=lfs diff=lfs merge=lfs -text +*.gz filter=lfs diff=lfs merge=lfs -text +*.h5 filter=lfs diff=lfs merge=lfs -text +*.joblib filter=lfs diff=lfs merge=lfs -text +*.lfs.* filter=lfs diff=lfs merge=lfs -text +*.mlmodel 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merge=lfs -text +*.zst filter=lfs diff=lfs merge=lfs -text +*tfevents* filter=lfs diff=lfs merge=lfs -text +VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.IQ4_XS.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q2_K.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_L.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_M.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_S.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q4_K_M.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q4_K_S.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q5_K_M.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q5_K_S.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q6_K.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q8_0.gguf filter=lfs diff=lfs merge=lfs -text +VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.f16.gguf filter=lfs diff=lfs merge=lfs -text diff --git a/README.md b/README.md new file mode 100644 index 0000000..77dcf44 --- /dev/null +++ b/README.md @@ -0,0 +1,76 @@ +--- +base_model: Nellyw888/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb +datasets: +- Nellyw888/RTL-Coder_7b_reasoning_tb +- Nellyw888/RTL-Coder_7b_reasoning_tb_simple +language: +- en +library_name: transformers +mradermacher: + readme_rev: 1 +quantized_by: mradermacher +tags: +- verilog +- reasoning +- reinforcement-learning +- rtl +--- +## About + + + + + + +static quants of https://huggingface.co/Nellyw888/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb + + + +***For a convenient overview and download list, visit our [model page for this model](https://hf.tst.eu/model#VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF).*** + +weighted/imatrix quants seem not to be available (by me) at this time. If they do not show up a week or so after the static ones, I have probably not planned for them. Feel free to request them by opening a Community Discussion. +## Usage + +If you are unsure how to use GGUF files, refer to one of [TheBloke's +READMEs](https://huggingface.co/TheBloke/KafkaLM-70B-German-V0.1-GGUF) for +more details, including on how to concatenate multi-part files. + +## Provided Quants + +(sorted by size, not necessarily quality. IQ-quants are often preferable over similar sized non-IQ quants) + +| Link | Type | Size/GB | Notes | +|:-----|:-----|--------:|:------| +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q2_K.gguf) | Q2_K | 1.4 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_S.gguf) | Q3_K_S | 1.6 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_M.gguf) | Q3_K_M | 1.7 | lower quality | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q3_K_L.gguf) | Q3_K_L | 1.8 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.IQ4_XS.gguf) | IQ4_XS | 1.9 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q4_K_S.gguf) | Q4_K_S | 1.9 | fast, recommended | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q4_K_M.gguf) | Q4_K_M | 2.0 | fast, recommended | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q5_K_S.gguf) | Q5_K_S | 2.3 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q5_K_M.gguf) | Q5_K_M | 2.3 | | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q6_K.gguf) | Q6_K | 2.6 | very good quality | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.Q8_0.gguf) | Q8_0 | 3.4 | fast, best quality | +| [GGUF](https://huggingface.co/mradermacher/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb-GGUF/resolve/main/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.f16.gguf) | f16 | 6.3 | 16 bpw, overkill | + +Here is a handy graph by ikawrakow comparing some lower-quality quant +types (lower is better): + +![image.png](https://www.nethype.de/huggingface_embed/quantpplgraph.png) + +And here are Artefact2's thoughts on the matter: +https://gist.github.com/Artefact2/b5f810600771265fc1e39442288e8ec9 + +## FAQ / Model Request + +See https://huggingface.co/mradermacher/model_requests for some answers to +questions you might have and/or if you want some other model quantized. + +## Thanks + +I thank my company, [nethype GmbH](https://www.nethype.de/), for letting +me use its servers and providing upgrades to my workstation to enable +this work in my free time. + + diff --git a/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.IQ4_XS.gguf b/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.IQ4_XS.gguf new file mode 100644 index 0000000..3000e72 --- /dev/null +++ b/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb.IQ4_XS.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:65251c5fdfe1be9bc10cc73d475b7bbf775b5e43721310496224aa989c962746 +size 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