mradermacher/Qwen-2.5-Instruct-Verilog-Reasoning-v2-7B-GGUF
1
0
Fork 0
Code Issues Pull Requests Actions Projects Releases Wiki Activity

初始化项目，由ModelHub XC社区提供模型

Browse Source 
Model: mradermacher/Qwen-2.5-Instruct-Verilog-Reasoning-v2-7B-GGUF
Source: Original Platform
This commit is contained in:
ModelHub XC
2026-05-26 02:47:15 +08:00
commit be74c331a4
14 changed files with 152 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
Qwen-2.5-Instruct-Verilog-Reasoning-v2-7B.Q8_0.gguf Normal file
View File

@@ -0,0 +1,3 @@
version https://git-lfs.github.com/spec/v1
oid sha256:b512a9a20a14e39a51cd08879913fb0904632b7c64317c26bf1a5a7604f94c4f
size 8098525664