Qwen-2.5-Instruct-Verilog-7…/Qwen-2.5-Instruct-Verilog-7B.f16.gguf

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初始化项目，由ModelHub XC社区提供模型 Model: mradermacher/Qwen-2.5-Instruct-Verilog-7B-GGUF Source: Original Platform 2026-05-09 06:45:56 +08:00			`version https://git-lfs.github.com/spec/v1`
			`oid sha256:a17898fd786ee92e714b4337d776949d75a47e02bfa77575e7946a5d2caa72ce`
			`size 15237853568`