From ab2a6c78a9981cec8ac7036c27ec19824375ee5f Mon Sep 17 00:00:00 2001 From: ModelHub XC Date: Tue, 26 May 2026 04:46:16 +0800 Subject: [PATCH] =?UTF-8?q?=E5=88=9D=E5=A7=8B=E5=8C=96=E9=A1=B9=E7=9B=AE?= =?UTF-8?q?=EF=BC=8C=E7=94=B1ModelHub=20XC=E7=A4=BE=E5=8C=BA=E6=8F=90?= =?UTF-8?q?=E4=BE=9B=E6=A8=A1=E5=9E=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Model: mradermacher/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B-GGUF Source: Original Platform --- .gitattributes | 47 +++++++++++++ ...ified-Verilog-Reasoning-GEN-7B.IQ4_XS.gguf | 3 + ...erified-Verilog-Reasoning-GEN-7B.Q2_K.gguf | 3 + ...ified-Verilog-Reasoning-GEN-7B.Q3_K_L.gguf | 3 + ...ified-Verilog-Reasoning-GEN-7B.Q3_K_M.gguf | 3 + ...ified-Verilog-Reasoning-GEN-7B.Q3_K_S.gguf | 3 + ...ified-Verilog-Reasoning-GEN-7B.Q4_K_M.gguf | 3 + ...ified-Verilog-Reasoning-GEN-7B.Q4_K_S.gguf | 3 + ...ified-Verilog-Reasoning-GEN-7B.Q5_K_M.gguf | 3 + ...ified-Verilog-Reasoning-GEN-7B.Q5_K_S.gguf | 3 + ...erified-Verilog-Reasoning-GEN-7B.Q6_K.gguf | 3 + ...erified-Verilog-Reasoning-GEN-7B.Q8_0.gguf | 3 + ...verified-Verilog-Reasoning-GEN-7B.f16.gguf | 3 + README.md | 69 +++++++++++++++++++ 14 files changed, 152 insertions(+) create mode 100644 .gitattributes create mode 100644 Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.IQ4_XS.gguf create mode 100644 Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q2_K.gguf create mode 100644 Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q3_K_L.gguf create mode 100644 Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q3_K_M.gguf create mode 100644 Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q3_K_S.gguf create mode 100644 Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q4_K_M.gguf create mode 100644 Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q4_K_S.gguf create mode 100644 Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q5_K_M.gguf create mode 100644 Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q5_K_S.gguf create mode 100644 Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q6_K.gguf create mode 100644 Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q8_0.gguf create mode 100644 Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.f16.gguf create mode 100644 README.md diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..83981d1 --- /dev/null +++ b/.gitattributes @@ -0,0 +1,47 @@ +*.7z filter=lfs diff=lfs merge=lfs -text +*.arrow filter=lfs diff=lfs merge=lfs -text +*.bin filter=lfs diff=lfs merge=lfs -text +*.bz2 filter=lfs diff=lfs merge=lfs -text +*.ckpt filter=lfs diff=lfs merge=lfs -text +*.ftz filter=lfs diff=lfs merge=lfs -text +*.gz filter=lfs diff=lfs merge=lfs -text +*.h5 filter=lfs diff=lfs merge=lfs -text +*.joblib filter=lfs diff=lfs merge=lfs -text +*.lfs.* filter=lfs diff=lfs merge=lfs -text +*.mlmodel filter=lfs diff=lfs merge=lfs -text +*.model filter=lfs diff=lfs merge=lfs -text +*.msgpack filter=lfs diff=lfs merge=lfs -text +*.npy filter=lfs diff=lfs merge=lfs -text +*.npz filter=lfs diff=lfs merge=lfs -text +*.onnx filter=lfs diff=lfs merge=lfs -text +*.ot filter=lfs diff=lfs merge=lfs -text +*.parquet filter=lfs diff=lfs merge=lfs -text +*.pb filter=lfs diff=lfs merge=lfs -text +*.pickle filter=lfs diff=lfs merge=lfs -text +*.pkl filter=lfs diff=lfs merge=lfs -text +*.pt filter=lfs diff=lfs merge=lfs -text +*.pth filter=lfs diff=lfs merge=lfs -text +*.rar filter=lfs diff=lfs merge=lfs -text +*.safetensors filter=lfs diff=lfs merge=lfs -text +saved_model/**/* filter=lfs diff=lfs merge=lfs -text +*.tar.* filter=lfs diff=lfs merge=lfs -text +*.tar filter=lfs diff=lfs merge=lfs -text +*.tflite filter=lfs diff=lfs merge=lfs -text +*.tgz filter=lfs diff=lfs merge=lfs -text +*.wasm filter=lfs diff=lfs merge=lfs -text +*.xz filter=lfs diff=lfs merge=lfs -text +*.zip filter=lfs diff=lfs merge=lfs -text +*.zst filter=lfs diff=lfs merge=lfs -text +*tfevents* filter=lfs diff=lfs merge=lfs -text +Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q4_K_S.gguf filter=lfs diff=lfs merge=lfs -text +Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q2_K.gguf filter=lfs diff=lfs merge=lfs -text +Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.f16.gguf filter=lfs diff=lfs merge=lfs -text +Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q8_0.gguf filter=lfs diff=lfs merge=lfs -text +Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q6_K.gguf filter=lfs diff=lfs merge=lfs -text +Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q3_K_M.gguf filter=lfs diff=lfs merge=lfs -text +Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q3_K_S.gguf filter=lfs diff=lfs merge=lfs -text +Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q3_K_L.gguf filter=lfs diff=lfs merge=lfs -text +Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q4_K_M.gguf filter=lfs diff=lfs merge=lfs -text +Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q5_K_S.gguf filter=lfs diff=lfs merge=lfs -text +Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q5_K_M.gguf filter=lfs diff=lfs merge=lfs -text +Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.IQ4_XS.gguf filter=lfs diff=lfs merge=lfs -text diff --git a/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.IQ4_XS.gguf b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.IQ4_XS.gguf new file mode 100644 index 0000000..400d289 --- /dev/null +++ b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.IQ4_XS.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:6fe65bdaa4a00a6eea875ed0833db426c3920c0efeced371817f8aff56f2dfe3 +size 4250298848 diff --git a/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q2_K.gguf b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q2_K.gguf new file mode 100644 index 0000000..042447a --- /dev/null +++ b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q2_K.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3fa6fa90db8cbe48c8980c7a5b6fffe4782b3953ef46442fc5ffbfd55bda4ca7 +size 3015940576 diff --git a/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q3_K_L.gguf b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q3_K_L.gguf new file mode 100644 index 0000000..47f22ae --- /dev/null +++ b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q3_K_L.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:633f08efab1527c63f54271aa9915309311609b02e66f61b6f721485994098ec +size 4088459744 diff --git a/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q3_K_M.gguf b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q3_K_M.gguf new file mode 100644 index 0000000..77ae839 --- /dev/null +++ b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q3_K_M.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:865e3ea93c64fc140bd67c700759e8edb385f6bf2834f6033f824a7486ef2752 +size 3808391648 diff --git a/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q3_K_S.gguf b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q3_K_S.gguf new file mode 100644 index 0000000..7268157 --- /dev/null +++ b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q3_K_S.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:d6151aaef88e9cb58fe26fafefc59cc6e5d761b3c9d2161d4d35e450ad239217 +size 3492368864 diff --git a/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q4_K_M.gguf b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q4_K_M.gguf new file mode 100644 index 0000000..98be7ac --- /dev/null +++ b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q4_K_M.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3d4f1fa610e67b89204078b1c7bd5fd5388f5fc1f3cfb8f94ba458b846ba3b8f +size 4683074016 diff --git a/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q4_K_S.gguf b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q4_K_S.gguf new file mode 100644 index 0000000..8261224 --- /dev/null +++ b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q4_K_S.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:f1e2bde2b7ce67e21e92fedb5c47a7d20f337e864aa91a2f65d13af2351d4583 +size 4457769440 diff --git a/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q5_K_M.gguf b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q5_K_M.gguf new file mode 100644 index 0000000..8201a62 --- /dev/null +++ b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q5_K_M.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:76b9eaad3f0deb9d5dd3b1707c646af64f786d7d700f658ccc8607900716e73c +size 5444831712 diff --git a/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q5_K_S.gguf b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q5_K_S.gguf new file mode 100644 index 0000000..b50ae92 --- /dev/null +++ b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q5_K_S.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:79cd86bade4783c84d170a269364ad7c46703d5f0d4e16bc42392427f0c75b3f +size 5315176928 diff --git a/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q6_K.gguf b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q6_K.gguf new file mode 100644 index 0000000..83ff6fa --- /dev/null +++ b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q6_K.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c4a7a9b7ce14651f713ae16b083bbd1ad1e85ca6ed553a47867ecaa750a067b1 +size 6254199264 diff --git a/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q8_0.gguf b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q8_0.gguf new file mode 100644 index 0000000..61ebffc --- /dev/null +++ b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q8_0.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:4d6bf77775a4e79e61f18262654da66f972ef0513008c201fe5690960b702465 +size 8098525664 diff --git a/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.f16.gguf b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.f16.gguf new file mode 100644 index 0000000..fecb6e4 --- /dev/null +++ b/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.f16.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:00638590e968cca0e2af55f2ec0685381f8dd6154dd0dd431c5be9755b3d4999 +size 15237853664 diff --git a/README.md b/README.md new file mode 100644 index 0000000..9a8104e --- /dev/null +++ b/README.md @@ -0,0 +1,69 @@ +--- +base_model: nyu-dice-lab/VeriThoughts-Reasoning-7B +language: +- en +library_name: transformers +mradermacher: + readme_rev: 1 +quantized_by: mradermacher +tags: [] +--- +## About + + + + + + +static quants of https://huggingface.co/nyu-dice-lab/VeriThoughts-Reasoning-7B + + + +***For a convenient overview and download list, visit our [model page for this model](https://hf.tst.eu/model#Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B-GGUF).*** + +weighted/imatrix quants seem not to be available (by me) at this time. If they do not show up a week or so after the static ones, I have probably not planned for them. Feel free to request them by opening a Community Discussion. +## Usage + +If you are unsure how to use GGUF files, refer to one of [TheBloke's +READMEs](https://huggingface.co/TheBloke/KafkaLM-70B-German-V0.1-GGUF) for +more details, including on how to concatenate multi-part files. + +## Provided Quants + +(sorted by size, not necessarily quality. IQ-quants are often preferable over similar sized non-IQ quants) + +| Link | Type | Size/GB | Notes | +|:-----|:-----|--------:|:------| +| [GGUF](https://huggingface.co/mradermacher/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B-GGUF/resolve/main/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q2_K.gguf) | Q2_K | 3.1 | | +| [GGUF](https://huggingface.co/mradermacher/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B-GGUF/resolve/main/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q3_K_S.gguf) | Q3_K_S | 3.6 | | +| [GGUF](https://huggingface.co/mradermacher/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B-GGUF/resolve/main/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q3_K_M.gguf) | Q3_K_M | 3.9 | lower quality | +| [GGUF](https://huggingface.co/mradermacher/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B-GGUF/resolve/main/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q3_K_L.gguf) | Q3_K_L | 4.2 | | +| [GGUF](https://huggingface.co/mradermacher/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B-GGUF/resolve/main/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.IQ4_XS.gguf) | IQ4_XS | 4.4 | | +| [GGUF](https://huggingface.co/mradermacher/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B-GGUF/resolve/main/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q4_K_S.gguf) | Q4_K_S | 4.6 | fast, recommended | +| [GGUF](https://huggingface.co/mradermacher/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B-GGUF/resolve/main/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q4_K_M.gguf) | Q4_K_M | 4.8 | fast, recommended | +| [GGUF](https://huggingface.co/mradermacher/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B-GGUF/resolve/main/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q5_K_S.gguf) | Q5_K_S | 5.4 | | +| [GGUF](https://huggingface.co/mradermacher/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B-GGUF/resolve/main/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q5_K_M.gguf) | Q5_K_M | 5.5 | | +| [GGUF](https://huggingface.co/mradermacher/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B-GGUF/resolve/main/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q6_K.gguf) | Q6_K | 6.4 | very good quality | +| [GGUF](https://huggingface.co/mradermacher/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B-GGUF/resolve/main/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.Q8_0.gguf) | Q8_0 | 8.2 | fast, best quality | +| [GGUF](https://huggingface.co/mradermacher/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B-GGUF/resolve/main/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B.f16.gguf) | f16 | 15.3 | 16 bpw, overkill | + +Here is a handy graph by ikawrakow comparing some lower-quality quant +types (lower is better): + +![image.png](https://www.nethype.de/huggingface_embed/quantpplgraph.png) + +And here are Artefact2's thoughts on the matter: +https://gist.github.com/Artefact2/b5f810600771265fc1e39442288e8ec9 + +## FAQ / Model Request + +See https://huggingface.co/mradermacher/model_requests for some answers to +questions you might have and/or if you want some other model quantized. + +## Thanks + +I thank my company, [nethype GmbH](https://www.nethype.de/), for letting +me use its servers and providing upgrades to my workstation to enable +this work in my free time. + +