Model synced from source: mradermacher/Qwen3-8B-Blunt-v5-GGUF
Updated 2026-05-26 04:57:18 +08:00
Model synced from source: osanseviero/mistral-instruct-frankenmerge
Updated 2026-05-26 04:47:19 +08:00
Model synced from source: brucewayne0459/OpenBioLLm-Derm
Updated 2026-05-26 04:46:22 +08:00
Model synced from source: mradermacher/ReMUD-7B-GGUF
Updated 2026-05-26 04:46:19 +08:00
Model synced from source: mradermacher/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GEN-7B-GGUF
Updated 2026-05-26 04:46:19 +08:00
Model synced from source: mradermacher/GRLHF-7B-Pretrained-GGUF
Updated 2026-05-26 04:46:19 +08:00
Model synced from source: mradermacher/Qwen3-8B-Blunt-Uncensor-v2-GGUF
Updated 2026-05-26 04:35:17 +08:00
Model synced from source: mradermacher/GRLHF-2B-Pretrained-SafeRLHF-GGUF
Updated 2026-05-26 04:34:18 +08:00
Model synced from source: ahelkadyy/Qwen3-8B-UnBias-Plus-SFT-Instruct-v2
Updated 2026-05-26 04:34:18 +08:00
Model synced from source: longtermrisk/Qwen3-8B-counterfactual-extended-facts-middle-third
Updated 2026-05-26 04:34:18 +08:00
Model synced from source: mradermacher/Qwen2.5-1.5B-Math-R1-GRPO-GGUF
Updated 2026-05-26 04:34:18 +08:00
Model synced from source: gregdlg/qwen-2.5-3b-r1-countdown-coloc
Updated 2026-05-26 04:26:20 +08:00
Model synced from source: ayoolaolafenwa/ChatLM
Updated 2026-05-26 04:23:19 +08:00
Model synced from source: kairawal/Llama-3.1-8B-Instruct-ZH-SynthDolly-r16alpha32-E3-S73
Updated 2026-05-26 04:23:18 +08:00
Model synced from source: kairawal/Llama-3.1-8B-Instruct-GA-SynthDolly-r16alpha32-E3-S73
Updated 2026-05-26 04:23:18 +08:00
Model synced from source: mradermacher/UltraIF-8B-UltraComposer-GGUF
Updated 2026-05-26 04:22:19 +08:00
Model synced from source: mradermacher/Sam-reason-v3-GGUF
Updated 2026-05-26 04:22:19 +08:00
Model synced from source: mradermacher/Reasoning-Mistral-Nemo-GGUF
Updated 2026-05-26 04:22:19 +08:00
Model synced from source: mradermacher/EduGemma4b-GGUF
Updated 2026-05-26 04:22:19 +08:00
Model synced from source: mradermacher/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GT-7B-GGUF
Updated 2026-05-26 04:21:20 +08:00