5f880bb279
The core of muh is now C++ headers that mirror CCCL's tuning architecture:
muh/include/muh/
├── hardware.cuh — hardware_capability descriptor (replaces cuda::compute_capability)
├── muh.cuh — top-level include + scoring formula
└── tuning/
├── common.cuh — shared types, compatible with CCCL's common.cuh
├── tuning_reduce.cuh — P0: attention reduction (5 type specializations)
├── tuning_topk.cuh — P0: sampling top-k/top-p (2B/4B key specializations)
├── tuning_scan.cuh — P0: prefix scan (6 lookback + 6 lookahead specializations)
├── tuning_transform.cuh — P1: activation elementwise (SiLU/GELU/RMSNorm)
├── tuning_batch_memcpy.cuh — P1: KV cache block copy
└── tuning_for.cuh — P2: RoPE position encoding
Architecture:
- Each tuning header has a policy_selector struct with operator()(hardware_capability)
- Dispatches on muh::hardware_capability instead of cuda::compute_capability
- bi100_* structs hold per-type tuning values (initialized from CCCL SM100 reference)
- When CCCL headers are available, re-exports their enum types
- When standalone, provides compatible enum definitions
Python files (extract.py, parse.py, gen_yaml.py, gen_patch.py) remain as tooling.
The C++ headers are what actually gets compiled into the vllm binary.
63 lines
2.4 KiB
Plaintext
63 lines
2.4 KiB
Plaintext
// muh/include/muh/hardware.cuh — Iluvatar BI-V100 hardware descriptor
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//
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// This header replaces cuda::compute_capability as the dispatch key.
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// CCCL's policy_selector uses operator()(cuda::compute_capability cc)
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// to select tuning params. muh's policy_selector uses
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// operator()(muh::hardware_capability hw) instead.
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#pragma once
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namespace muh {
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/// Hardware capability descriptor for non-NVIDIA GPUs.
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/// Replaces cuda::compute_capability {major, minor} with a richer
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/// description that captures what actually matters for kernel tuning.
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struct hardware_capability {
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int warp_size; // threads per warp (NVIDIA=32, BI-V100=TBD)
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int max_threads_per_block; // max CTA size (typically 1024)
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int max_shared_memory_per_block; // bytes of shared memory per block
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int max_registers_per_thread; // max registers per thread
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int l2_cache_size_bytes; // L2 cache size in bytes
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int memory_bandwidth_gbps; // HBM bandwidth in GB/s
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int sm_count; // number of SMs / compute units
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// For dispatch: identifies which tuning table to use
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enum class vendor_t { nvidia, iluvatar, unknown };
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vendor_t vendor;
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int arch_version; // e.g. 100 for BI-V100
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// Convenience constructors
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constexpr static hardware_capability bi_v100() {
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return {
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.warp_size = 32, // TBD: confirm on actual hardware
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.max_threads_per_block = 1024,
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.max_shared_memory_per_block = 49152, // 48 KiB, TBD
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.max_registers_per_thread = 255,
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.l2_cache_size_bytes = 6 * 1024 * 1024, // 6 MiB, TBD
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.memory_bandwidth_gbps = 900, // TBD
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.sm_count = 50, // 50c in the spec
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.vendor = vendor_t::iluvatar,
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.arch_version = 100,
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};
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}
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// Comparison for dispatch: exact match on vendor + arch
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constexpr bool operator==(const hardware_capability& o) const {
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return vendor == o.vendor && arch_version == o.arch_version;
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}
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constexpr bool operator!=(const hardware_capability& o) const {
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return !(*this == o);
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}
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// Check if this hardware is "at least" a given capability
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// For same vendor, compares arch_version
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constexpr bool at_least(vendor_t v, int min_arch) const {
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return vendor == v && arch_version >= min_arch;
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}
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};
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/// Global default target — set to BI-V100 for competition
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inline constexpr auto target_hw = hardware_capability::bi_v100();
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} // namespace muh
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