Files
project_6_89d52222/muh/include/muh/tuning/tuning_adjacent_difference.cuh
dylanyunlon 12ad7a3190 [muh] 7 headers 完整移植 CCCL tuning tables: segmented_sort 7%→29%, merge_sort 22%→43%, merge 30%→49%, adjacent_difference 38%→65%, batch_memcpy 37%→41%, find 35%→43%, find_bound 31%→44%
每个文件都是直接 cat 读完整 CCCL 源码后理解全部参数语义,
然后用大模型生成 BI-V100 适配版本。不使用 grep/sed/批量脚本。

segmented_sort.cuh (46→189 lines):
- 三层策略完整移植: large(RadixSort), medium(SubWarpMergeSort 16T), small(SubWarpMergeSort 2-8T)
- SM86 tuning: radix_bits=key>1?6:4, scale_reg_bound(256,23)
- BI-V100 SMEM cap for all three tiers

merge_sort.cuh (43→83 lines):
- SM50{256,11} SM52{512,15} SM60+{256,17} 三代参数
- nominal_4b_items_to_items scaling + unroll flag

merge.cuh (55→89 lines):
- SM52/SM60/SM80/SM90/SM100 五代参数
- bulk_copy=false (BI-V100 无 cp.async.bulk)

adjacent_difference.cuh (46→77 lines):
- nominal_8b_items_to_items(7) scaling
- may_alias → LOAD_CA vs LOAD_LDG

batch_memcpy.cuh (86→95 lines):
- small{128T,4buf,8B} + large{256T,32B} 双策略
- prefer_pow2_bits=false (SM70+)

find.cuh (32→39 lines):
- scale_mem_bound(128,16) + vec_size=4

find_bound_sorted_values.cuh (33→47 lines):
- SM80+: {512, N4B(15)} / SM60+: {256} / SM50: LOAD_LDG
2026-08-03 21:36:50 +00:00

78 lines
2.8 KiB
Plaintext

// muh/include/muh/tuning/tuning_adjacent_difference.cuh — BI-V100
//
// Mirrors: cccl_upstream/cub/cub/device/dispatch/tuning/tuning_adjacent_difference.cuh
// CCCL source: 118 lines. Single policy for all compute capabilities.
//
// CCCL policy_selector (all CC):
// {128, Nominal8BItems(7, value_size), WARP_TRANSPOSE, may_alias?LOAD_CA:LOAD_LDG, WARP_TRANSPOSE}
//
// Nominal8BItemsToItems(7, value_size) = max(1, 7 * 8 / value_size)
// 1B → 56, 2B → 28, 4B → 14, 8B → 7, 16B → 3
//
// vllm relevance: computing token-level delta logits for speculative decoding,
// detecting attention pattern changes between consecutive positions.
//
// SMEM: threads * items * value_size * 2 (BlockLoad + BlockStore, double buffer)
// BI-V100 48KB limit → cap items when value_size is large.
#pragma once
#include "muh/hardware.cuh"
#include "muh/tuning/common.cuh"
namespace muh::tuning::adjacent_difference {
// ============================================================================
// Policy struct — matches CCCL AdjacentDifferencePolicy exactly
// ============================================================================
struct AdjacentDifferencePolicy {
int threads_per_block;
int items_per_thread;
BlockLoadAlgorithm load_algorithm;
CacheLoadModifier load_modifier;
BlockStoreAlgorithm store_algorithm;
};
// ============================================================================
// Helper: nominal_8B_items_to_items (from CCCL util_device.cuh)
// Scales items from an 8-byte nominal to actual value_size
// ============================================================================
constexpr int nominal_8b_items(int nominal, int value_size) {
int result = nominal * 8 / value_size;
return result > 0 ? result : 1;
}
// ============================================================================
// policy_selector — single policy for all CC (matches CCCL)
// BI-V100 SMEM cap applied for large items
// ============================================================================
struct policy_selector {
int value_type_size;
bool may_alias;
constexpr AdjacentDifferencePolicy operator()(const hardware_capability& hw) const {
int items = nominal_8b_items(7, value_type_size);
// SMEM check: BlockLoad + BlockStore share tile through union
// tile = threads * items * value_type_size
int threads = 128;
int tile_smem = threads * items * value_type_size;
while (tile_smem > hw.max_shared_memory_per_block - 2048 && items > 1) {
items--;
tile_smem = threads * items * value_type_size;
}
return AdjacentDifferencePolicy{
threads, items,
BLOCK_LOAD_WARP_TRANSPOSE,
may_alias ? LOAD_CA : LOAD_LDG,
BLOCK_STORE_WARP_TRANSPOSE
};
}
};
} // namespace muh::tuning::adjacent_difference