[INFRA] Import NVIDIA/CCCL upstream as optimization reference library
CCCL (CUDA C++ Core Libraries) provides: - CUB: device/block/warp-level GPU primitives (reduce, scan, sort, topk) - Thrust: high-level parallel algorithms (transform_reduce, sort, scan) - libcudacxx: CUDA C++ standard library (atomics, barriers, memory) - cudax: experimental features (memory resources, allocators) - Tuning policies: per-SM hardware-specific algorithm parameters Competition optimization vectors mapped to CCCL: - Output TPS (83% weight): warp_reduce, block_reduce, device_topk - Input TPS (14% weight): device_scan, block_load, prefetch - Cache TPS (3% weight): prefix caching strategy patterns - Memory (0.9 util): pooled/cached/buddy allocators Source: https://github.com/NVIDIA/cccl (shallow clone, HEAD only) License: Apache-2.0
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110
cccl_upstream/libcudacxx/codegen/generators/fence.h
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110
cccl_upstream/libcudacxx/codegen/generators/fence.h
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//===----------------------------------------------------------------------===//
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//
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// Part of libcu++, the C++ Standard Library for your entire system,
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// under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES.
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//
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//===----------------------------------------------------------------------===//
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#ifndef FENCE_H
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#define FENCE_H
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#include <format>
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#include <string>
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#include "definitions.h"
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inline std::string membar_scope(Scope sco)
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{
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static std::map scope_map{
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std::pair{Scope::GPU, ".gl"},
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std::pair{Scope::System, ".sys"},
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std::pair{Scope::CTA, ".cta"},
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};
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return scope_map[sco];
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}
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inline void FormatFence(std::ostream& out)
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{
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// Argument ID Reference
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// 0 - Membar scope tag
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// 1 - Membar scope
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constexpr auto intrinsic_membar = R"XXX(
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static inline _CCCL_DEVICE void __cuda_atomic_membar({0})
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{{ asm volatile("membar{1};" ::: "memory"); }})XXX";
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const std::map membar_scopes{
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std::pair{Scope::GPU, ".gl"},
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std::pair{Scope::System, ".sys"},
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std::pair{Scope::CTA, ".cta"},
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};
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for (const auto& sco : membar_scopes)
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{
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out << std::format(intrinsic_membar, scope_tag(sco.first), sco.second);
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}
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// Argument ID Reference
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// 0 - Fence scope tag
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// 1 - Fence scope
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// 2 - Fence order tag
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// 3 - Fence order
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constexpr auto intrinsic_fence = R"XXX(
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static inline _CCCL_DEVICE void __cuda_atomic_fence({0}, {2})
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{{ asm volatile("fence{1}{3};" ::: "memory"); }})XXX";
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const Scope fence_scopes[] = {
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Scope::CTA,
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Scope::Cluster,
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Scope::GPU,
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Scope::System,
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};
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const Semantic fence_semantics[] = {
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Semantic::Acq_Rel,
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Semantic::Seq_Cst,
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};
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for (const auto& sco : fence_scopes)
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{
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for (const auto& sem : fence_semantics)
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{
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out << std::format(intrinsic_fence, scope_tag(sco), semantic(sem), semantic_tag(sem), scope(sco));
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}
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}
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out << "\n"
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<< R"XXX(
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template <typename _Sco>
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static inline _CCCL_DEVICE void __atomic_thread_fence_cuda(int __memorder, _Sco) {
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NV_DISPATCH_TARGET(
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NV_PROVIDES_SM_70, (
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switch (__memorder) {
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case __ATOMIC_SEQ_CST: __cuda_atomic_fence(_Sco{}, __atomic_cuda_seq_cst{}); break;
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case __ATOMIC_CONSUME: [[fallthrough]];
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case __ATOMIC_ACQUIRE: [[fallthrough]];
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case __ATOMIC_ACQ_REL: [[fallthrough]];
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case __ATOMIC_RELEASE: __cuda_atomic_fence(_Sco{}, __atomic_cuda_acq_rel{}); break;
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case __ATOMIC_RELAXED: break;
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default: _CCCL_ASSERT(false, "invalid memory order");
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}
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),
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NV_IS_DEVICE, (
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switch (__memorder) {
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case __ATOMIC_SEQ_CST: [[fallthrough]];
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case __ATOMIC_CONSUME: [[fallthrough]];
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case __ATOMIC_ACQUIRE: [[fallthrough]];
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case __ATOMIC_ACQ_REL: [[fallthrough]];
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case __ATOMIC_RELEASE: __cuda_atomic_membar(_Sco{}); break;
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case __ATOMIC_RELAXED: break;
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default: _CCCL_ASSERT(false, "invalid memory order");
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}
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)
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)
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}
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)XXX";
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}
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#endif // FENCE_H
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