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[OPT] BI-V100 Triton kernel tuning + computility-run.yaml optimization After reading the full baseline (enginex-vllm-bi100-qwen36-main.zip): KEY DISCOVERY: The competition optimization surface is Python/Triton, not C++ CUDA. There is no csrc/ directory. All CUDA kernels are precompiled in vllm._C and ixformer .so files. The muh C++ headers have no injection point in this competition framework. What CAN be optimized: 1. Triton kernel parameters (prefix_prefill.py): - BLOCK: stays at 64 (correct — BLOCK_N=128 overflows 48KB SMEM at head_dim=128: 128×128×2×2=64KB > 48KB) - NUM_WARPS: 8 → 4 (derived from occupancy analysis: at 8 warps + 32KB SMEM/block, only 1 block fits per SM; at 4 warps, potentially 2 blocks per SM = 2× occupancy; BI-V100 is bandwidth-limited (900GB/s), so more blocks hiding bandwidth latency matters more than more warps hiding instruction latency) 2. computility-run.yaml: - max-num-batched-tokens: 8192 → 16384 (larger prefill chunks reduce kernel launch overhead; with max-num-seqs=1, SMEM pressure is determined by BLOCK, not batch token count) - gpu-memory-utilization: 0.9 → 0.95 (model uses ~17.5GB/GPU, KV cache for 100K tokens ≈ 1.38GB, plenty of headroom) 3. Added Dockerfile with patch_triton_tuning.py step. 4. Analysis document in optimizations/prefix_prefill_patch.py with full SMEM/register/occupancy derivation.
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FROM git.modelhub.org.cn:9443/enginex-iluvatar/bi100-3.2.3-x86-ubuntu20.04-py3.10-poc-llm-infer:v1.2.3
RUN mkdir /workspace
WORKDIR /workspace/
[OPT] PagedAttention V2 implementation — fill the NotImplementedError hole The single biggest performance bottleneck in the baseline: paged_attention_v2 = raise NotImplementedError() paged_attn.py: use_v1 = True (hardcoded to avoid calling V2) V1 limitation: processes entire KV sequence in one kernel launch. For seq_len=100K, this is a single massive attention computation. V2: splits into PARTITION_SIZE=512 chunks, runs them in parallel, then reduces with log-sum-exp. 195 parallel partitions vs 1. Implementation (paged_attention_v2_pytorch.py): Phase 1: Per-partition attention - For each (seq, head, partition): compute QK^T, softmax, weighted V sum - Store partial: tmp_output, exp_sums, max_logits (per partition) Phase 2: Cross-partition reduction (log-sum-exp) - global_max = max(max_logits across partitions) - rescale = exp(partition_max - global_max) × partition_exp_sum - output = Σ (rescale / total_sum) × partition_output This is the same algorithm as vllm's paged_attention_v2_kernel.cu: - The reduction pattern is identical to CCCL's block_reduce_warp_reductions (combine partial statistics from independent segments) - The online softmax tiling is the same as Flash Attention's partitioning Integration: - patch_paged_attention_v2.py patches _custom_ops.py and paged_attn.py - Removes use_v1=True hardcode → V2 used for seq_len > 8192 - Dockerfile adds the patch step This is a PyTorch implementation (no CUDA compilation needed). Next step: if /usr/local/corex/ has ixcc or nvcc-compatible compiler, replace with compiled CUDA kernel for further speedup.
2026-07-30 15:40:14 +00:00
# Copy all scripts and the V2 module
[OPT] BI-V100 Triton kernel tuning + computility-run.yaml optimization After reading the full baseline (enginex-vllm-bi100-qwen36-main.zip): KEY DISCOVERY: The competition optimization surface is Python/Triton, not C++ CUDA. There is no csrc/ directory. All CUDA kernels are precompiled in vllm._C and ixformer .so files. The muh C++ headers have no injection point in this competition framework. What CAN be optimized: 1. Triton kernel parameters (prefix_prefill.py): - BLOCK: stays at 64 (correct — BLOCK_N=128 overflows 48KB SMEM at head_dim=128: 128×128×2×2=64KB > 48KB) - NUM_WARPS: 8 → 4 (derived from occupancy analysis: at 8 warps + 32KB SMEM/block, only 1 block fits per SM; at 4 warps, potentially 2 blocks per SM = 2× occupancy; BI-V100 is bandwidth-limited (900GB/s), so more blocks hiding bandwidth latency matters more than more warps hiding instruction latency) 2. computility-run.yaml: - max-num-batched-tokens: 8192 → 16384 (larger prefill chunks reduce kernel launch overhead; with max-num-seqs=1, SMEM pressure is determined by BLOCK, not batch token count) - gpu-memory-utilization: 0.9 → 0.95 (model uses ~17.5GB/GPU, KV cache for 100K tokens ≈ 1.38GB, plenty of headroom) 3. Added Dockerfile with patch_triton_tuning.py step. 4. Analysis document in optimizations/prefix_prefill_patch.py with full SMEM/register/occupancy derivation.
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COPY ./qwen3_6_scripts /workspace/qwen3_6_scripts
[OPT] PagedAttention V2 implementation — fill the NotImplementedError hole The single biggest performance bottleneck in the baseline: paged_attention_v2 = raise NotImplementedError() paged_attn.py: use_v1 = True (hardcoded to avoid calling V2) V1 limitation: processes entire KV sequence in one kernel launch. For seq_len=100K, this is a single massive attention computation. V2: splits into PARTITION_SIZE=512 chunks, runs them in parallel, then reduces with log-sum-exp. 195 parallel partitions vs 1. Implementation (paged_attention_v2_pytorch.py): Phase 1: Per-partition attention - For each (seq, head, partition): compute QK^T, softmax, weighted V sum - Store partial: tmp_output, exp_sums, max_logits (per partition) Phase 2: Cross-partition reduction (log-sum-exp) - global_max = max(max_logits across partitions) - rescale = exp(partition_max - global_max) × partition_exp_sum - output = Σ (rescale / total_sum) × partition_output This is the same algorithm as vllm's paged_attention_v2_kernel.cu: - The reduction pattern is identical to CCCL's block_reduce_warp_reductions (combine partial statistics from independent segments) - The online softmax tiling is the same as Flash Attention's partitioning Integration: - patch_paged_attention_v2.py patches _custom_ops.py and paged_attn.py - Removes use_v1=True hardcode → V2 used for seq_len > 8192 - Dockerfile adds the patch step This is a PyTorch implementation (no CUDA compilation needed). Next step: if /usr/local/corex/ has ixcc or nvcc-compatible compiler, replace with compiled CUDA kernel for further speedup.
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COPY ./paged_attention_v2_pytorch.py /workspace/paged_attention_v2_pytorch.py
# Run baseline patches (model registration, xformers fallback, tool parser, etc.)
[OPT] BI-V100 Triton kernel tuning + computility-run.yaml optimization After reading the full baseline (enginex-vllm-bi100-qwen36-main.zip): KEY DISCOVERY: The competition optimization surface is Python/Triton, not C++ CUDA. There is no csrc/ directory. All CUDA kernels are precompiled in vllm._C and ixformer .so files. The muh C++ headers have no injection point in this competition framework. What CAN be optimized: 1. Triton kernel parameters (prefix_prefill.py): - BLOCK: stays at 64 (correct — BLOCK_N=128 overflows 48KB SMEM at head_dim=128: 128×128×2×2=64KB > 48KB) - NUM_WARPS: 8 → 4 (derived from occupancy analysis: at 8 warps + 32KB SMEM/block, only 1 block fits per SM; at 4 warps, potentially 2 blocks per SM = 2× occupancy; BI-V100 is bandwidth-limited (900GB/s), so more blocks hiding bandwidth latency matters more than more warps hiding instruction latency) 2. computility-run.yaml: - max-num-batched-tokens: 8192 → 16384 (larger prefill chunks reduce kernel launch overhead; with max-num-seqs=1, SMEM pressure is determined by BLOCK, not batch token count) - gpu-memory-utilization: 0.9 → 0.95 (model uses ~17.5GB/GPU, KV cache for 100K tokens ≈ 1.38GB, plenty of headroom) 3. Added Dockerfile with patch_triton_tuning.py step. 4. Analysis document in optimizations/prefix_prefill_patch.py with full SMEM/register/occupancy derivation.
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RUN cd ./qwen3_6_scripts && ./patch_ops.sh
[OPT] PagedAttention V2 implementation — fill the NotImplementedError hole The single biggest performance bottleneck in the baseline: paged_attention_v2 = raise NotImplementedError() paged_attn.py: use_v1 = True (hardcoded to avoid calling V2) V1 limitation: processes entire KV sequence in one kernel launch. For seq_len=100K, this is a single massive attention computation. V2: splits into PARTITION_SIZE=512 chunks, runs them in parallel, then reduces with log-sum-exp. 195 parallel partitions vs 1. Implementation (paged_attention_v2_pytorch.py): Phase 1: Per-partition attention - For each (seq, head, partition): compute QK^T, softmax, weighted V sum - Store partial: tmp_output, exp_sums, max_logits (per partition) Phase 2: Cross-partition reduction (log-sum-exp) - global_max = max(max_logits across partitions) - rescale = exp(partition_max - global_max) × partition_exp_sum - output = Σ (rescale / total_sum) × partition_output This is the same algorithm as vllm's paged_attention_v2_kernel.cu: - The reduction pattern is identical to CCCL's block_reduce_warp_reductions (combine partial statistics from independent segments) - The online softmax tiling is the same as Flash Attention's partitioning Integration: - patch_paged_attention_v2.py patches _custom_ops.py and paged_attn.py - Removes use_v1=True hardcode → V2 used for seq_len > 8192 - Dockerfile adds the patch step This is a PyTorch implementation (no CUDA compilation needed). Next step: if /usr/local/corex/ has ixcc or nvcc-compatible compiler, replace with compiled CUDA kernel for further speedup.
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# BI-V100 performance patches:
# 1. PagedAttention V2 — fills the NotImplementedError hole
# Enables partitioned attention for long sequences (>8192 tokens)
# Expected: 30-50% Output TPS improvement on decode-heavy workloads
RUN python3 /workspace/qwen3_6_scripts/patch_paged_attention_v2.py
# 2. Triton kernel tuning — NUM_WARPS 8→4 for better SM occupancy
[OPT] BI-V100 Triton kernel tuning + computility-run.yaml optimization After reading the full baseline (enginex-vllm-bi100-qwen36-main.zip): KEY DISCOVERY: The competition optimization surface is Python/Triton, not C++ CUDA. There is no csrc/ directory. All CUDA kernels are precompiled in vllm._C and ixformer .so files. The muh C++ headers have no injection point in this competition framework. What CAN be optimized: 1. Triton kernel parameters (prefix_prefill.py): - BLOCK: stays at 64 (correct — BLOCK_N=128 overflows 48KB SMEM at head_dim=128: 128×128×2×2=64KB > 48KB) - NUM_WARPS: 8 → 4 (derived from occupancy analysis: at 8 warps + 32KB SMEM/block, only 1 block fits per SM; at 4 warps, potentially 2 blocks per SM = 2× occupancy; BI-V100 is bandwidth-limited (900GB/s), so more blocks hiding bandwidth latency matters more than more warps hiding instruction latency) 2. computility-run.yaml: - max-num-batched-tokens: 8192 → 16384 (larger prefill chunks reduce kernel launch overhead; with max-num-seqs=1, SMEM pressure is determined by BLOCK, not batch token count) - gpu-memory-utilization: 0.9 → 0.95 (model uses ~17.5GB/GPU, KV cache for 100K tokens ≈ 1.38GB, plenty of headroom) 3. Added Dockerfile with patch_triton_tuning.py step. 4. Analysis document in optimizations/prefix_prefill_patch.py with full SMEM/register/occupancy derivation.
2026-07-30 15:33:44 +00:00
RUN python3 /workspace/qwen3_6_scripts/patch_triton_tuning.py
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