47 lines
1.5 KiB
Plaintext
47 lines
1.5 KiB
Plaintext
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// muh/include/muh/tuning/tuning_adjacent_difference.cuh — BI-V100
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//
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// Mirrors: cccl_upstream/cub/cub/device/dispatch/tuning/tuning_adjacent_difference.cuh
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// CCCL: single policy for all architectures. No SM100 specialization.
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// threads=128, items=nominal_8B_items_to_items(7, value_size), WARP_TRANSPOSE, LDG/CA
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//
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// vllm relevance: low (KV cache delta encoding, not on hot path)
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// SMEM risk: 128*items*value_size — at value_size=8, items=7, tile=7168 ≤ 49152 ✓
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#pragma once
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#include "muh/hardware.cuh"
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#include "muh/tuning/common.cuh"
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namespace muh::tuning::adjacent_difference {
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struct AdjacentDifferencePolicy {
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int threads_per_block;
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int items_per_thread;
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BlockLoadAlgorithm load_algorithm;
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CacheLoadModifier load_modifier;
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BlockStoreAlgorithm store_algorithm;
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};
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// CCCL's nominal_8B_items_to_items: scale items for non-8B types
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// items = max(1, nominal_8B_items * 8 / value_type_size)
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constexpr int nominal_8B_items(int nominal, int value_size) {
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int items = nominal * 8 / value_size;
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return items < 1 ? 1 : items;
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}
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struct policy_selector {
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int value_type_size;
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bool may_alias;
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constexpr AdjacentDifferencePolicy operator()(const hardware_capability& /*hw*/) const {
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// CCCL uses the same policy for all architectures
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return {128,
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nominal_8B_items(7, value_type_size),
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BLOCK_LOAD_WARP_TRANSPOSE,
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may_alias ? LOAD_CA : LOAD_LDG,
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BLOCK_STORE_WARP_TRANSPOSE};
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}
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};
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} // namespace muh::tuning::adjacent_difference
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