284804ac53
Sources: siboehm/SGEMM_CUDA → upstream_ref/sgemm_siboehm/ (25 files) wangzyon/NVIDIA_SGEMM_PRACTICE → upstream_ref/nvidia_sgemm_practice/ (23 files, filled gaps) edtallison/sgemm-cuda → upstream_ref/sgemm_edtallison/ (41 files) All files cat'd one by one from git clone (no --depth). These are the 3 public SGEMM repos that can compile on CUDA 10.2 + CoreX ivcore10. Key files for BI-V100 porting: kernel 10 (warp tiling) — already proven on device with WARPSIZE=64 kernel 11/12 (double buffering) — next optimization target sgemm.cu + runner.cu — complete build+benchmark harness CMakeLists.txt — build system reference
47 lines
1.1 KiB
Plaintext
47 lines
1.1 KiB
Plaintext
#include <cuda_runtime.h>
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#include <iostream>
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#include <vector>
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__global__ void kernel(uint *A, uint *B, int row) {
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auto x = threadIdx.x / 4;
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auto y = threadIdx.x % 4;
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A[x * row + y] = x;
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B[x * row + y] = y;
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}
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int main(int argc, char **argv) {
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uint *Xs, *Ys;
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uint *Xs_d, *Ys_d;
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uint SIZE = 4;
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Xs = (uint *)malloc(SIZE * SIZE * sizeof(uint));
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Ys = (uint *)malloc(SIZE * SIZE * sizeof(uint));
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cudaMalloc((void **)&Xs_d, SIZE * SIZE * sizeof(uint));
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cudaMalloc((void **)&Ys_d, SIZE * SIZE * sizeof(uint));
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dim3 grid_size(1, 1, 1);
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dim3 block_size(4 * 4);
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kernel<<<grid_size, block_size>>>(Xs_d, Ys_d, 4);
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cudaMemcpy(Xs, Xs_d, SIZE * SIZE * sizeof(uint), cudaMemcpyDeviceToHost);
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cudaMemcpy(Ys, Ys_d, SIZE * SIZE * sizeof(uint), cudaMemcpyDeviceToHost);
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cudaDeviceSynchronize();
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for (int row = 0; row < SIZE; ++row) {
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for (int col = 0; col < SIZE; ++col) {
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std::cout << "[" << Xs[row * SIZE + col] << "|" << Ys[row * SIZE + col]
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<< "] ";
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}
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std::cout << "\n";
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}
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cudaFree(Xs_d);
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cudaFree(Ys_d);
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free(Xs);
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free(Ys);
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}
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