Sources (Apache 2.0, cloned 2026-08-09): - Deep-Spark/xllm: Iluvatar's official C++ inference engine - Deep-Spark/vllm: Iluvatar's vllm fork Key files for our EX Engine development: MoE topk_softmax (fixes 2304 calls/token PyTorch fallback): - xllm/kernels/cuda/moe/moe_topk_softmax_kernels.cuh CUB-based fused softmax+topk, power-of-2 expert count optimized For 64 experts: topk_gating_softmax<T,VPT=2,64,WARPS=4,BYTES=4> - xllm/kernels/ilu/ixformer.h Official ixformer C++ API: topk_softmax(), paged_attention(), etc. - xllm/kernels/ilu/fused_moe.cpp How xllm calls ixformer::infer::topk_softmax() - ds_vllm/csrc/moe/topk_softmax_kernels.cu vllm-native topk_softmax (TensorRT-LLM derived, 874 lines) GatedDeltaNet (fixes NaN in 4 GDN layers): - xllm/layers/npu_torch/qwen3_gated_delta_net_base.cpp fp32 state accumulation, proper recurrent update Complete FusedMoE pipeline reference: - xllm/layers/ilu/fused_moe.cpp gate -> topk -> expand -> gemm1 -> act -> gemm2 -> combine
184 lines
7.0 KiB
Plaintext
184 lines
7.0 KiB
Plaintext
/* Copyright 2025 The vLLM Authors and The xLLM Authors. All Rights Reserved.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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https://github.com/jd-opensource/xllm/blob/main/LICENSE
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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==============================================================================*/
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#include <c10/cuda/CUDAGuard.h>
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#include <torch/cuda.h>
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#include "cuda_ops_api.h"
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// ref to:
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// https://github.com/vllm-project/vllm/blob/main/csrc/activation_kernels.cu
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namespace {
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// Use read-only cache load for CUDA kernels.
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#define XLLM_LDG(arg) __ldg(arg)
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template <typename scalar_t,
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scalar_t (*ACT_FN)(const scalar_t&),
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bool act_first>
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__device__ __forceinline__ scalar_t compute(const scalar_t& x,
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const scalar_t& y) {
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return act_first ? ACT_FN(x) * y : x * ACT_FN(y);
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}
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// Check if pointer is 16-byte aligned for int4 vectorized access
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__device__ __forceinline__ bool is_16byte_aligned(const void* ptr) {
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return (reinterpret_cast<uintptr_t>(ptr) & 15) == 0;
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}
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// Activation and gating kernel template with 128-bit vectorized access
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// optimization.
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template <typename scalar_t,
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scalar_t (*ACT_FN)(const scalar_t&),
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bool act_first>
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__global__ void act_and_mul_kernel(
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scalar_t* __restrict__ out, // [..., d]
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const scalar_t* __restrict__ input, // [..., 2, d]
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const int d) {
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constexpr int VEC_SIZE = 16 / sizeof(scalar_t);
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const int64_t token_idx = blockIdx.x;
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const scalar_t* x_ptr = input + token_idx * 2 * d;
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const scalar_t* y_ptr = x_ptr + d;
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scalar_t* out_ptr = out + token_idx * d;
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// Check alignment for 128-bit vectorized access.
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// All three pointers must be 16-byte aligned for safe int4 operations.
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const bool aligned = is_16byte_aligned(x_ptr) && is_16byte_aligned(y_ptr) &&
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is_16byte_aligned(out_ptr);
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if (aligned && d >= VEC_SIZE) {
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// Fast path: 128-bit vectorized loop
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const int4* x_vec = reinterpret_cast<const int4*>(x_ptr);
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const int4* y_vec = reinterpret_cast<const int4*>(y_ptr);
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int4* out_vec = reinterpret_cast<int4*>(out_ptr);
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const int num_vecs = d / VEC_SIZE;
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const int vec_end = num_vecs * VEC_SIZE;
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for (int i = threadIdx.x; i < num_vecs; i += blockDim.x) {
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int4 x = XLLM_LDG(&x_vec[i]), y = XLLM_LDG(&y_vec[i]), r;
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auto* xp = reinterpret_cast<scalar_t*>(&x);
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auto* yp = reinterpret_cast<scalar_t*>(&y);
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auto* rp = reinterpret_cast<scalar_t*>(&r);
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#pragma unroll
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for (int j = 0; j < VEC_SIZE; j++) {
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rp[j] = compute<scalar_t, ACT_FN, act_first>(xp[j], yp[j]);
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}
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out_vec[i] = r;
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}
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// Scalar cleanup for remaining elements
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for (int i = vec_end + threadIdx.x; i < d; i += blockDim.x) {
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out_ptr[i] = compute<scalar_t, ACT_FN, act_first>(XLLM_LDG(&x_ptr[i]),
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XLLM_LDG(&y_ptr[i]));
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}
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} else {
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// Scalar fallback for unaligned data or small d
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for (int64_t idx = threadIdx.x; idx < d; idx += blockDim.x) {
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const scalar_t x = XLLM_LDG(&x_ptr[idx]);
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const scalar_t y = XLLM_LDG(&y_ptr[idx]);
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out_ptr[idx] = compute<scalar_t, ACT_FN, act_first>(x, y);
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}
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}
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}
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template <typename T>
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__device__ __forceinline__ T silu_kernel(const T& x) {
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// x * sigmoid(x)
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return (T)(((float)x) / (1.0f + expf((float)-x)));
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}
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template <typename T>
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__device__ __forceinline__ T gelu_kernel(const T& x) {
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// Equivalent to PyTorch GELU with 'none' approximation.
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// Refer to:
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// https://github.com/pytorch/pytorch/blob/8ac9b20d4b090c213799e81acf48a55ea8d437d6/aten/src/ATen/native/cuda/ActivationGeluKernel.cu#L36-L38
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const float f = (float)x;
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constexpr float ALPHA = M_SQRT1_2;
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return (T)(f * 0.5f * (1.0f + ::erf(f * ALPHA)));
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}
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template <typename T>
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__device__ __forceinline__ T gelu_tanh_kernel(const T& x) {
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// Equivalent to PyTorch GELU with 'tanh' approximation.
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// Refer to:
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// https://github.com/pytorch/pytorch/blob/8ac9b20d4b090c213799e81acf48a55ea8d437d6/aten/src/ATen/native/cuda/ActivationGeluKernel.cu#L25-L30
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const float f = (float)x;
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constexpr float BETA = M_SQRT2 * M_2_SQRTPI * 0.5f;
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constexpr float KAPPA = 0.044715;
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float x_cube = f * f * f;
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float inner = BETA * (f + KAPPA * x_cube);
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return (T)(0.5f * f * (1.0f + ::tanhf(inner)));
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}
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#define LAUNCH_ACTIVATION_GATE_KERNEL(KERNEL, ACT_FIRST) \
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int d = input.size(-1) / 2; \
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int64_t num_tokens = input.numel() / input.size(-1); \
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dim3 grid(num_tokens); \
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dim3 block(std::min(d, 1024)); \
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if (num_tokens == 0) { \
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return; \
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} \
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const at::cuda::OptionalCUDAGuard device_guard(device_of(input)); \
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const cudaStream_t stream = at::cuda::getCurrentCUDAStream(); \
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DISPATCH_FLOATING_TYPES(input.scalar_type(), "act_and_mul_kernel", [&] { \
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act_and_mul_kernel<scalar_t, KERNEL<scalar_t>, ACT_FIRST> \
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<<<grid, block, 0, stream>>>( \
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out.data_ptr<scalar_t>(), input.data_ptr<scalar_t>(), d); \
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});
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void silu_and_mul(torch::Tensor out, // [..., d]
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torch::Tensor input) // [..., 2 * d]
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{
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LAUNCH_ACTIVATION_GATE_KERNEL(silu_kernel, true);
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}
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void gelu_and_mul(torch::Tensor& out, // [..., d]
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torch::Tensor& input) // [..., 2 * d]
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{
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LAUNCH_ACTIVATION_GATE_KERNEL(gelu_kernel, true);
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}
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void gelu_tanh_and_mul(torch::Tensor& out, // [..., d]
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torch::Tensor& input) // [..., 2 * d]
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{
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LAUNCH_ACTIVATION_GATE_KERNEL(gelu_tanh_kernel, true);
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}
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} // namespace
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namespace xllm::kernel::cuda {
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void act_and_mul(torch::Tensor out,
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torch::Tensor input,
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const std::string& act_mode) {
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if (act_mode != "silu" && act_mode != "gelu" && act_mode != "gelu_tanh") {
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LOG(FATAL) << "Unsupported act mode: " << act_mode
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<< ", only support silu, gelu, gelu_tanh";
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}
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// flashinfer act_and_mul ops
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// std::string uri = act_mode + "_and_mul";
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// FunctionFactory::get_instance().act_and_mul(uri).call(
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// out, input, support_pdl());
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if (act_mode == "silu") {
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silu_and_mul(out, input);
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} else if (act_mode == "gelu") {
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gelu_and_mul(out, input);
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} else if (act_mode == "gelu_tanh") {
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gelu_tanh_and_mul(out, input);
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}
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}
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} // namespace xllm::kernel::cuda
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