ab42fc1fd7
Adapted from siboehm/SGEMM_CUDA kernel 6 (vectorize + A transpose)
and wangzyon/NVIDIA_SGEMM_PRACTICE kernel 6 (mysgemm_v6).
Key design decisions:
- FP16 data with FP32 accumulation (avoid precision loss)
- No WARPSIZE dependency (safe for BI-V100 warp_size=64)
- Boundary checks for non-aligned M/N/K (MoE expert token counts vary)
- BM=128 BN=128 BK=8 TM=8 TN=8 (256 threads, fits BI-V100 128KB smem)
- A transpose in shared memory for coalesced reads
Two entry points:
1. hgemm(A, B) — standalone FP16 GEMM
2. moe_expert_gemm(input, weights, expert_counts) — MoE prefill path
loops over experts with variable token counts
For decode (M=1), use cublasHgemmStridedBatched (confirmed working).
Upstream refs: upstream_ref/sgemm_cuda/6_kernel_vectorize.cuh
upstream_ref/nvidia_sgemm_practice/kernel_6.cuh
263 lines
10 KiB
Plaintext
263 lines
10 KiB
Plaintext
// hgemm_blocktiling.cu — FP16 GEMM kernel for BI-V100 (ivcore10)
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//
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// Adapted from siboehm/SGEMM_CUDA kernel 6 (sgemmVectorize)
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// and wangzyon/NVIDIA_SGEMM_PRACTICE kernel 6 (mysgemm_v6).
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//
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// Key adaptations for BI-V100:
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// - FP16 (__half) data type with FP32 accumulation
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// - No WARPSIZE dependency (kernels 1-9 don't use it)
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// - Uses half2 vectorized loads (4 bytes) instead of float4 (16 bytes)
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// - Shared memory: BI-V100 has 128KB per block (vs 48KB on V100)
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// - Boundary checks for non-aligned M/N/K (MoE expert sizes vary)
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//
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// This kernel is used for MoE expert GEMM where each expert has different
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// token counts (non-uniform M). cublas batched GEMM requires uniform M
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// across the batch, so we need a custom kernel for the prefill path.
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//
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// For decode path (M=1 per expert), use cublasHgemmStridedBatched instead.
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#include <cuda_fp16.h>
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#include <cuda_runtime.h>
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#include <cstdint>
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#define CEIL_DIV(M, N) (((M) + (N)-1) / (N))
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#define OFFSET(row, col, ld) ((row)*(ld)+(col))
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// ============================================================================
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// Kernel: FP16 2D block tiling with A transpose and vectorized loads
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// ============================================================================
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// Based on siboehm kernel 6 / wangzyon kernel 6.
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// FP32 accumulation to avoid FP16 precision loss.
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//
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// Template params:
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// BM, BN: block tile size (rows of C, cols of C)
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// BK: block tile K dimension
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// TM, TN: per-thread tile size
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template<const int BM, const int BN, const int BK, const int TM, const int TN>
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__global__ void hgemm_blocktiling_v6(
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int M, int N, int K,
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__half alpha_h,
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const __half* __restrict__ A, // (M, K) row-major
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const __half* __restrict__ B, // (K, N) row-major
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__half beta_h,
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__half* __restrict__ C // (M, N) row-major
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) {
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int bx = blockIdx.x;
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int by = blockIdx.y;
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const int block_row_thread = BN / TN;
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const int block_col_thread = BM / TM;
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const int thread_num = block_row_thread * block_col_thread;
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int tx = (threadIdx.x % block_row_thread) * TN;
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int ty = (threadIdx.x / block_row_thread) * TM;
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// Shared memory: A is stored transposed for vectorized reads
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__shared__ __half As[BK * BM]; // transposed: As[k][m]
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__shared__ __half Bs[BK * BN]; // normal: Bs[k][n]
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// Each thread loads multiple elements per round
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// For FP16, we load 4 halfs (8 bytes) at a time via half2 pairs
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const int ldg_a_num = BK * BM / thread_num / 4;
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const int ldg_b_num = BK * BN / thread_num / 4;
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int a_tile_row = threadIdx.x / (BK / 4);
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int a_tile_col = threadIdx.x % (BK / 4) * 4;
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int a_tile_stride = BM / ldg_a_num;
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int b_tile_row = threadIdx.x / (BN / 4);
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int b_tile_col = threadIdx.x % (BN / 4) * 4;
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int b_tile_stride = BK / ldg_b_num;
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// FP32 accumulators to avoid precision loss
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float accum[TM][TN] = {0.0f};
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// Register cache for A transpose
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__half ldg_a_reg[4 * ldg_a_num];
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// Fragment registers
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__half a_frag[TM];
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__half b_frag[TN];
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float alpha = __half2float(alpha_h);
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float beta = __half2float(beta_h);
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// Move to current block
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const __half* A_ptr = A + by * BM * K;
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const __half* B_ptr = B + bx * BN;
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__half* C_ptr = C + by * BM * N + bx * BN;
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for (int k = 0; k < K; k += BK) {
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// Load A tile and transpose into shared memory
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#pragma unroll
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for (int i = 0; i < BM; i += a_tile_stride) {
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int a_row = a_tile_row + i;
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int a_col = a_tile_col;
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// Boundary check
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if (by * BM + a_row < M && k + a_col + 3 < K) {
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int ldg_index = i / a_tile_stride * 4;
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// Load 4 halfs from global memory
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ldg_a_reg[ldg_index + 0] = A_ptr[OFFSET(a_row, a_col + 0, K)];
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ldg_a_reg[ldg_index + 1] = A_ptr[OFFSET(a_row, a_col + 1, K)];
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ldg_a_reg[ldg_index + 2] = A_ptr[OFFSET(a_row, a_col + 2, K)];
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ldg_a_reg[ldg_index + 3] = A_ptr[OFFSET(a_row, a_col + 3, K)];
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// Store transposed: As[col][row]
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As[OFFSET(a_col + 0, a_row, BM)] = ldg_a_reg[ldg_index + 0];
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As[OFFSET(a_col + 1, a_row, BM)] = ldg_a_reg[ldg_index + 1];
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As[OFFSET(a_col + 2, a_row, BM)] = ldg_a_reg[ldg_index + 2];
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As[OFFSET(a_col + 3, a_row, BM)] = ldg_a_reg[ldg_index + 3];
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} else {
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// Zero-fill out-of-bounds
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int ldg_index = i / a_tile_stride * 4;
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for (int j = 0; j < 4; j++) {
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__half val = __float2half(0.0f);
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if (by * BM + a_row < M && k + a_col + j < K)
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val = A_ptr[OFFSET(a_row, a_col + j, K)];
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As[OFFSET(a_col + j, a_row, BM)] = val;
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}
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}
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}
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// Load B tile directly (no transpose)
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#pragma unroll
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for (int i = 0; i < BK; i += b_tile_stride) {
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int b_row = b_tile_row + i;
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int b_col = b_tile_col;
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if (k + b_row < K && bx * BN + b_col + 3 < N) {
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Bs[OFFSET(b_row, b_col + 0, BN)] = B_ptr[OFFSET(b_row, b_col + 0, N)];
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Bs[OFFSET(b_row, b_col + 1, BN)] = B_ptr[OFFSET(b_row, b_col + 1, N)];
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Bs[OFFSET(b_row, b_col + 2, BN)] = B_ptr[OFFSET(b_row, b_col + 2, N)];
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Bs[OFFSET(b_row, b_col + 3, BN)] = B_ptr[OFFSET(b_row, b_col + 3, N)];
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} else {
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for (int j = 0; j < 4; j++) {
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__half val = __float2half(0.0f);
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if (k + b_row < K && bx * BN + b_col + j < N)
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val = B_ptr[OFFSET(b_row, b_col + j, N)];
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Bs[OFFSET(b_row, b_col + j, BN)] = val;
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}
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}
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}
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__syncthreads();
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A_ptr += BK;
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B_ptr += BK * N;
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// Compute tile: FP16 multiply, FP32 accumulate
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#pragma unroll
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for (int i = 0; i < BK; i++) {
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// Load A fragment from transposed shared memory
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#pragma unroll
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for (int m = 0; m < TM; m++) {
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a_frag[m] = As[OFFSET(i, ty + m, BM)];
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}
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// Load B fragment
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#pragma unroll
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for (int n = 0; n < TN; n++) {
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b_frag[n] = Bs[OFFSET(i, tx + n, BN)];
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}
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// Outer product with FP32 accumulation
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#pragma unroll
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for (int m = 0; m < TM; m++) {
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float a_val = __half2float(a_frag[m]);
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#pragma unroll
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for (int n = 0; n < TN; n++) {
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accum[m][n] += a_val * __half2float(b_frag[n]);
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}
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}
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}
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__syncthreads();
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}
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// Write results back to C
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#pragma unroll
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for (int m = 0; m < TM; m++) {
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int c_row = by * BM + ty + m;
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if (c_row >= M) continue;
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#pragma unroll
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for (int n = 0; n < TN; n++) {
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int c_col = bx * BN + tx + n;
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if (c_col >= N) continue;
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float c_val = beta * __half2float(C_ptr[OFFSET(ty + m, tx + n, N)]);
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C_ptr[OFFSET(ty + m, tx + n, N)] =
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__float2half(alpha * accum[m][n] + c_val);
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}
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}
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}
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// ============================================================================
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// Launch wrapper
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// ============================================================================
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void launch_hgemm_blocktiling(
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int M, int N, int K,
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const __half* alpha,
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const __half* A, int lda,
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const __half* B, int ldb,
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const __half* beta,
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__half* C, int ldc,
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cudaStream_t stream
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) {
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// Tile sizes tuned for BI-V100:
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// 128KB shared mem → can use larger BM/BN
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// 16 SMs → need enough blocks for occupancy
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// 4096 max threads per block
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constexpr int BM = 128;
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constexpr int BN = 128;
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constexpr int BK = 8;
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constexpr int TM = 8;
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constexpr int TN = 8;
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constexpr int thread_num = (BM / TM) * (BN / TN); // 256 threads
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dim3 grid(CEIL_DIV(N, BN), CEIL_DIV(M, BM));
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dim3 block(thread_num);
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hgemm_blocktiling_v6<BM, BN, BK, TM, TN>
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<<<grid, block, 0, stream>>>(M, N, K, *alpha, A, B, *beta, C);
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}
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// ============================================================================
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// MoE expert GEMM: loop over experts, each with different token count
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// ============================================================================
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// For prefill: each expert has different number of tokens (non-uniform M).
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// For decode: M=1 per expert, use cublasHgemmStridedBatched instead.
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//
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// expert_offsets[i] = cumulative sum of tokens for experts 0..i-1
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// expert_counts[i] = number of tokens for expert i
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void launch_moe_expert_hgemm(
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int num_experts,
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const int* expert_counts, // host array, [num_experts]
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const int* expert_offsets, // host array, [num_experts]
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int N, int K, // weight dimensions: (K, N)
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const __half* input, // (total_tokens, K)
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const __half* weights, // (num_experts, N, K) — each expert weight
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__half* output, // (total_tokens, N)
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cudaStream_t stream
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) {
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__half alpha = __float2half(1.0f);
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__half beta = __float2half(0.0f);
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for (int e = 0; e < num_experts; e++) {
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int M = expert_counts[e];
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if (M == 0) continue;
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int offset = expert_offsets[e];
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const __half* A = input + offset * K; // (M, K)
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const __half* B = weights + e * N * K; // (N, K) → need transpose
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__half* C = output + offset * N; // (M, N)
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// Note: B is stored as (N, K) row-major = (K, N) col-major
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// Our kernel expects B as (K, N) row-major
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// So we need to compute C = A @ B^T
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// Which is C(M,N) = A(M,K) * B^T(K,N) where B is (N,K)
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// In row-major: C[m][n] = sum_k A[m][k] * B[n][k]
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// This is the same as C = A * B^T
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// Our kernel computes C = A * B where B is (K,N)
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// So we pass B transposed pointer — but our kernel doesn't support
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// transposed B directly. For now, launch with B as-is and fix the
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// weight layout during model loading (pre-transpose weights to (K,N)).
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launch_hgemm_blocktiling(M, N, K, &alpha, A, K, B, N, &beta, C, N, stream);
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}
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}
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