f4e2264a83
Copied from upstream_ref (NOT rewritten — exact upstream code):
ixformer C++ API (the authoritative header):
include/ixformer.h — ixformer::infer namespace: topk_softmax,
moe_compute_token_index_api, moe_w16a16_group_gemm, moe_expand_input,
moe_output_reduce_sum, silu_and_mul, rms_norm, xllm_paged_attention, etc.
include/ilu_ops_api.h — xllm::kernel::ilu namespace: moe_active_topk,
moe_gen_idx, moe_expand_input, group_gemm, moe_combine_result,
batch_prefill, batch_decode, rms_norm, matmul, act_and_mul, etc.
ILU kernel wrappers (call ixformer::infer directly):
csrc/ilu_kernel_fused_moe.cpp — topk routing + gen_idx + expand + combine
csrc/ilu_kernel_group_gemm.cpp — batched expert GEMM
csrc/ilu_kernel_{activation,norm,rope,matmul,attention}.cpp
ILU layer implementations (full pipeline):
csrc/ilu_layer_fused_moe.{cpp,h} — 797 lines, the complete MoE pipeline
that competitor 168 ran as corex_moe.py
csrc/ilu_layer_attention.{cpp,h} — prefill/decode attention dispatch
CUDA MoE kernels (from xllm + ds_vllm):
csrc/moe/moe_topk_softmax_kernels.cuh — CUB BlockReduce + warp topk
csrc/moe/moe_topk_sigmoid_kernels.cuh — sigmoid scoring variant
csrc/moe/moe_topk.cuh + moe_fused_topk.cu — entry points
csrc/moe/moeTopKFuncs.cuh — TRT-LLM derived vllm-compatible topk
csrc/moe/moe_ops.h + moe_align_sum_kernels.cu — alignment kernels
Common layer headers:
csrc/common_fused_moe{,_base}.h + common_moe_fused_topk.{cpp,h}
74 lines
2.3 KiB
C++
74 lines
2.3 KiB
C++
/* Copyright 2025 The xLLM Authors. All Rights Reserved.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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https://github.com/jd-opensource/xllm/blob/main/LICENSE
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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==============================================================================*/
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#include "ilu_ops_api.h"
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#include "util/env_var.h"
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namespace xllm::kernel::ilu {
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bool gemv_conditions(const torch::Tensor& input,
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const torch::Tensor& weight,
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const torch::Tensor& bias,
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int64_t gemv_max_batch) {
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// gemv input:[m,k] weight:[n,k]
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// 1. m <= gemv_max_batch
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// 2. k % 32 == 0 && n % 2 == 0
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// 3. bias is None
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torch::Tensor input_view = input.view({-1, input.size(-1)});
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torch::Tensor weight_view = weight.view({-1, weight.size(-1)});
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int64_t m = input_view.size(0);
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int64_t k = input_view.size(1);
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int64_t n = weight_view.size(0);
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if (bias.defined() == false && m <= gemv_max_batch && k % 32 == 0 &&
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n % 2 == 0) {
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return true;
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}
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return false;
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}
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torch::Tensor matmul(torch::Tensor a,
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torch::Tensor b,
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std::optional<torch::Tensor> bias) {
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int64_t act_type = -1;
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bool persistent = false;
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std::vector<int64_t> output_shape = a.sizes().vec();
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if (!output_shape.empty()) {
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output_shape[output_shape.size() - 1] = b.size(0);
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}
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torch::Tensor output = a.new_empty(output_shape);
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bool use_gemv = true;
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const int64_t gemv_max_batch = 1;
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const bool disable_infer_gemm_ex =
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xllm::util::get_bool_env("DISABLE_INFER_GEMM_EX", false);
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use_gemv =
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use_gemv &&
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gemv_conditions(a, b, bias.value_or(at::Tensor()), gemv_max_batch) &&
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!disable_infer_gemm_ex && (act_type == -1);
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if (use_gemv) {
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output = infer::ixformer_linear_ex(a, b, bias, output);
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} else {
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output = infer::ixformer_linear(a, b, act_type, bias, output, persistent);
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}
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return output;
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}
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} // namespace xllm::kernel::ilu
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